AT45CS1282-TC Atmel, AT45CS1282-TC Datasheet
AT45CS1282-TC
Specifications of AT45CS1282-TC
Related parts for AT45CS1282-TC
AT45CS1282-TC Summary of contents
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... Program/Erase Cycles Per Sector Minimum • Data Retention – 10 Years • Commercial Temperature Range Description The AT45CS1282 is a 2.7-volt, dual-interface sequential access Flash memory ideally suited for infrequent code shadowing applications. This device utilizes Atmel’s - ™ e STAC Multi-Level Cell (MLC) memory technology, which allows a single cell to ...
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... RDY/BUSY SI SER/BYTE To provide optimal flexibility, the memory array of the AT45CS1282 is divided into two levels of granularity comprising of sectors, and pages. The “Memory Architecture Dia- gram” illustrates the breakdown of each level and details the number of pages per sector. All program operations to the DataFlash occur on a page by page basis. The erase operations is performed at the sector level ...
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... The first 14 bits (PA13 - PA0) of the AT45CS1282 [Preliminary] PAGE ARCHITECTURE 8 Pages ...
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... AT45CS1282 [Preliminary] 4 25-bit address sequence specify which page of the main memory array to read, and the last 11 bits (BA10 - BA0) of the 25-bit address sequence specify the starting byte address within the page. The don’t care clock cycles that follow the four address bytes are needed to initialize the read operation. Following the don’ ...
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... CS pin, the part will erase the selected sector. The erase operation is internally self-timed and should take place in a maximum time of t this time, the status register and the RDY/BUSY pin will indicate that the part is busy. AT45CS1282 [Preliminary] for fast programming. During this FP ...
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... Sector Erase Addressing PA13 PA12 PA11 PA10 • • • • • • • • • • • • Additional Commands AT45CS1282 [Preliminary] 6 PA9 PA8 PA7 PA6 PA5 • • • • • • • • • • • • • • • ...
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... The device density is indicated using bits and 2 of the status register. For the AT45CS1282, the four bits are The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices ...
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... Manufacturer ID codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7FH. A system should detect code 7FH as a “Continuation Code” and continue to read Manufacturer ID bytes. The first non-7FH byte would signify the last byte of Manufacturer ID data. For Atmel (and some other manufacturers), the Manufacturer ID data is comprised of only one byte. AT45CS1282 [Preliminary] 8 Bit 3 ...
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... Summary 3447A–DFLSH–2/04 The AT45CS1282 contains a specialized register that can be used for security purposes in system design. The Security Register is a unique 128-byte register that is divided into two portions. The first 64 bytes (byte 0 to byte 63) of this register are allocated as a one- time user programmable space ...
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... Pin Descriptions AT45CS1282 [Preliminary Group A mode is in progress (not fully completed), then another mode in Group A should not be started. However, during this time in which a Group A mode is in progress, modes in Group B can be started, except the first two Group A commands (Memory Array Read Commands). ...
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... Like all Flash memories, the peak current for DataFlash occur during the programming and erase operation. The regulator needs to supply this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during programming or erase can lead to improper operation and possible data corruption. AT45CS1282 [Preliminary ...
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... AT45CS1282 [Preliminary] 12 Table 1. Read Commands Command Main Memory Page Read Continuous Array Read Buffer 1 Read Buffer 2 Read Buffer 1 Read Buffer 2 Read Table 2. Program and Erase Commands Command Buffer 1 Write Buffer 2 Write Buffer 1 to Main Memory Page Program Buffer 1 to Main Memory Page Program, ...
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... P 89h 98h 99h 9Ah N/A 9Fh D2h D4h D6h N/A D7h E8h Notes Page Address Bit B = Byte/Buffer Address Bit x = Don’t Care *The number with (*) is for 8-bit interface. 3447A–DFLSH–2/04 AT45CS1282 [Preliminary] Address Byte Address Byte N/A N N/A N Address Byte Additional Don’ ...
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... Output Low Voltage OL V Output High Voltage OH Notes during a buffer read maximum. CC1 2. I during a buffer read maximum. CC2 AT45CS1282 [Preliminary] 14 *NOTICE: + 0.6V CC Com the minimum specified datasheet value, the system should wait 20 ms before an opera- CC Condition CS, RESET all IH inputs at CMOS levels MHz ...
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... XFR t Page Programming Time P t Fast Page Programming Time FP t Sector 0a Erase Time SE0a t Sector 0b-63 Erase Time SE0b-63 t RESET Pulse Width RST t RESET Recovery Time REC 3447A–DFLSH–2/04 AT45CS1282 [Preliminary] Min Typ Max 250 250 250 150 500 50 15 ...
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... Sector 0a Erase Time SE0a t Sector 0b-63 Erase Time SE0b-63 t RESET Pulse Width RST t RESET Recovery Time REC Input Test Waveforms and Measurement Levels DRIVING LEVELS Output Test Load AT45CS1282 [Preliminary] 16 2.4V AC 1.5V 0.45V < (10 DEVICE UNDER TEST 30 pF Min Typ ...
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... Waveform 5 and waveform 6 are for 8-bit Rapid8 interface over the full frequency range of operation (maximum frequency = 20 MHz CSS VALID OUT VALID CSS VALID OUT VALID IN AT45CS1282 [Preliminary] period. These timing waveforms are valid over CSH DIS HIGH IMPEDANCE CSH t DIS HIGH IMPEDANCE 17 ...
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... SO SI Waveform 4 – RapidS Mode 3 (for all Frequencies) CS SCK/CLK HIGH Waveform 5 – Rapid8 Mode SCK/CLK HIGH IMPEDANCE I/O7 - I/O0 (OUTPUT) I/O7 - I/O0 (INPUT) Waveform 6 – Rapid8 Mode SCK/CLK I/O7 - I/O0 (OUTPUT) I/O7 - I/O0 (INPUT) AT45CS1282 [Preliminary CSS VALID OUT VALID CSS WL ...
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... HIGH IMPEDANCE 8 bits CMD 8 bits 8 bits Page Address (PA13 - PA0) FLASH MEMORY ARRAY I/O INTERFACE SI AT45CS1282 [Preliminary] t REC t CSS t RST HIGH IMPEDANCE 8 bits LSB Byte/Buffer Address (BA10 - BA0/BFA10 - BFA0) BUFFER 2 TO MAIN MEMORY PAGE PROGRAM BUFFER 2 (1056 BYTES) ...
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... Each transition represents 8 bits Read Operations The following block diagram and waveforms illustrate the various read sequences available. PAGE (1056 BYTES) MAIN MEMORY BUFFER 1 (1056 BYTES) AT45CS1282 [Preliminary X···X, BFA10-8 BFA7-0 Starts self-timed erase/program operation CMD XXXXXXX PA13 ...
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... PA12-5 PA4-0, BA10-8 BA7-0 CMD XX...PA13 PA12-5 CMD X X X···X, BFA10-8 ADDR AT45CS1282 [Preliminary Cycles for Serial 19 Cycles for Parallel Starts reading page data into buffer PA4-0, XXX X X BFA7-0 1 Dummy Byte (Serial) ADDR 2 Dummy Bytes (Parallel) ...
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... Detailed Bit-level Read Timing – RapidS Serial Interface Mode 0 Continuous Array Read (Opcode: E8H) CS SCK HIGH IMPEDANCE SO Main Memory Page Read (Opcode: D2H) CS SCK COMMAND OPCODE AT45CS1282 [Preliminary DATA OUT HIGH IMPEDANCE LSB MSB BIT 8,447 BIT PAGE n PAGE n DATA OUT ...
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... SO Manufacturer and Device ID Read (Opcode: 9FH) CS SCK HIGH IMPEDANCE SO 3447A–DFLSH–2/ HIGH IMPEDANCE COMMAND OPCODE COMMAND OPCODE AT45CS1282 [Preliminary DATA OUT MSB STATUS REGISTER OUTPUT MSB DON’T CARE FOR FREQ. OVER 25 MHz PRODUCT ID OUTPUT MSB LSB LSB MSB MSB ...
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... Detailed Bit-level Read Timing – RapidS Serial Interface Mode 3 Continuous Array Read (Opcode: E8H) CS SCK HIGH IMPEDANCE SO Main Memory Page Read (Opcode: D2H) CS SCK COMMAND OPCODE AT45CS1282 [Preliminary DATA OUT HIGH IMPEDANCE LSB MSB BIT 8,447 BIT PAGE n PAGE n DATA OUT ...
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... SO Manufacturer and Device ID Read (Opcode: 9FH) CS SCK HIGH IMPEDANCE SO 3447A–DFLSH–2/ HIGH IMPEDANCE COMMAND OPCODE COMMAND OPCODE AT45CS1282 [Preliminary DATA OUT MSB STATUS REGISTER OUTPUT MSB LSB DON’T CARE FOR FREQ. OVER 25 MHz PRODUCT ID OUTPUT MSB LSB MSB 17 18 ...
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... Continuous Array Read (Opcode: E8H) CS CLK I/O7-I/O0 CMD ADDR (INPUT) I/O7-I/O0 HIGH IMPEDANCE (OUTPUT) Main Memory Page Read (Opcode: D2H) CS CLK COMMAND OPCODE I/O7-I/O0 CMD ADDR ADDR ADDR ADDR (INPUT) I/O7-I/O0 (OUTPUT) AT45CS1282 [Preliminary DATA OUT DATA DATA DATA HIGH IMPEDANCE 27 DATA ...
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... Detailed 8-bit Timing – Rapid8 Mode 0 (Continued) Buffer Read (Opcode: 54H or 56H) CS CLK t SU I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT) Status Register Read (Opcode: D7H) CS CLK I/O7-I/O0 (INPUT) HIGH IMPEDANCE I/O7-I/O0 (OUTPUT) 3447A–DFLSH–2/04 AT45CS1282 [Preliminary COMMAND OPCODE ADDR CMD X X ADDR HIGH IMPEDANCE CMD ...
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... Continuous Array Read (Opcode: E8H) CS CLK I/O7-I/O0 CMD ADDR (INPUT) HIGH IMPEDANCE I/O7-I/O0 (OUTPUT) Main Memory Page Read (Opcode: D2H) CS CLK I/07-I/O0 CMD (INPUT) I/07-I/O0 (OUTPUT) AT45CS1282 [Preliminary DATA OUT DATA DATA DATA COMMAND OPCODE ADDR ADDR ADDR ADDR X X HIGH IMPEDANCE ...
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... SU I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT) Status Register Read (Opcode: D7H) CS CLK I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT) 3447A–DFLSH–2/ CMD X X ADDR ADDR HIGH IMPEDANCE CMD t V HIGH X X DATA IMPEDANCE STATUS REGISTER OUTPUT AT45CS1282 [Preliminary DATA OUT DATA DATA DATA DATA 29 ...
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... Note: 1. RapidS Serial Interface. 40T 40-lead, ( mm) Plastic Thin Small Outline Package, Type I (TSOP) 44C2 44-ball mm) Plastic Chip-size Ball Grid Array Package (CBGA) AT45CS1282 [Preliminary] 30 Ordering Code AT45CS1282-TC AT45CS1282-CC Package Type Operation Range Package Commercial 40T (0° 70° C) Commercial 44C2 (0° 70° C) ...
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... Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R 3447A–DFLSH–2/04 PIN SEATING PLANE A1 TITLE 40T, 40-lead ( Package) Plastic Thin Small Outline Package, Type I (TSOP) AT45CS1282 [Preliminary] 0º ~ 8º GAGE PLANE COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM A – – ...
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... REF Bottom View 2325 Orchard Parkway San Jose, CA 95131 R AT45CS1282 [Preliminary Ball Corner 2.00 REF Øb TITLE 44C2, 44-ball ( Array 1.2 mm Body, 0.4 mm Ball Plastic Chip-scale Ball Grid Array Package (CBGA) 0.12 C Seating Plane Side View COMMON DIMENSIONS (Unit of Measure = mm) ...
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... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...