AT45CS1282-TC Atmel, AT45CS1282-TC Datasheet - Page 6

• Manufacturer Part Number: AT45CS1282-TC
• Description: IC FLASH 128MBIT 50MHZ 40TSOP
• Manufacturer: Atmel

Specifications of AT45CS1282-TC

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 128M (16,384 pages x 1056 bytes)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Sector Erase Addressing
Additional Commands
6
PA13
0
0
0
0
1
1
1
1
•
•
•
PA12
AT45CS1282 [Preliminary]
0
0
0
0
1
1
1
1
•
•
•
PA11
0
0
0
0
1
1
1
1
•
•
•
PA10
0
0
0
0
1
1
1
1
•
•
•
PA9
MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred
from the main memory to either buffer 1 or buffer 2. To start the operation, a 1-byte
opcode, 53H for buffer 1 and 55H for buffer 2, must be clocked into the device, followed
by four address bytes comprised of 7 don’t care bits, 14-page address bits (PA13- PA0),
which specify the page in main memory that is to be transferred, and 11 don’t care bits.
The CS pin must be low while toggling the SCK/CLK pin to load the opcode and the
address bytes from the input pins (SI or I/O7 - I/O0). The transfer of the page of data
from the main memory to the buffer will begin when the CS pin transitions from a low to
a high state. During the transfer of a page of data (t
or the RDY/BUSY can be monitored to determine whether the transfer has been
completed.
MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can
be compared to the data in buffer 1 or buffer 2. To initiate the operation, a 1-byte
opcode, 60H for buffer 1 and 61H for buffer 2, must be clocked into the device, followed
by four address bytes consisting of 7 don’t care bits, 14-page address bits (PA13 - PA0)
that specify the page in the main memory that is to be compared to the buffer, and 11
don’t care bits. The CS pin must be low while toggling the SCK/CLK pin to load the
opcode and the address bytes from the input pins (SI or I/O7 - I/O0). On the low-to-high
transition of the CS pin, the 1056 bytes in the selected main memory page will be com-
pared with the 1056 bytes in buffer 1 or buffer 2. During this time (t
register and the RDY/BUSY pin will indicate that the part is busy. On completion of the
compare operation, bit 6 of the status register is updated with the result of the compare.
STATUS REGISTER READ: The status register can be used to determine the device’s
ready/busy status, the result of a Main Memory Page to Buffer Compare operation, or
the device density. To read the status register, an opcode must be loaded into the
device. After the opcode and optional dummy byte(s) is clocked in, the 1-byte status
register will be clocked out on the output pins (SO or I/O7 - I/O0), starting with the next
clock cycle. In case of serial interface, opcode D7H is followed with an optional dummy
byte (8 clocks). For Serial applications over 25 MHz, opcode must be always followed
with a dummy byte. In case of applications with 8-bit interface, opcode D7H and two
dummy clock cycles should be used. When using the serial interface, the data in the sta-
tus register, starting with the MSB (bit 7), will be clocked out on the SO pin during the
next eight clock cycles.
0
0
0
1
0
0
1
1
•
•
•
PA8
0
0
1
0
0
1
0
1
•
•
•
PA7
X
X
X
X
X
X
X
0
•
•
•
PA6
0
X
X
X
X
X
X
X
•
•
•
PA5
X
X
X
X
X
X
X
0
•
•
•
PA4
X
X
X
X
X
X
X
0
•
•
•
PA3
0
X
X
X
X
X
X
X
•
•
•
XFR
), the status register can be read
PA2
X
X
X
X
X
X
X
X
•
•
•
PA1
X
X
X
X
X
X
X
X
•
•
•
XFR
PA0
3447A–DFLSH–2/04
X
X
X
X
X
X
X
X
•
•
•
), the status
Sector
0a
0b
60
61
62
63
1
2
•
•
•