AT49LH004-33JC SL383 Atmel, AT49LH004-33JC SL383 Datasheet - Page 14

• Manufacturer Part Number: AT49LH004-33JC SL383
• Description: IC FLASH 4MBIT 33MHZ 32PLCC
• Manufacturer: Atmel

Specifications of AT49LH004-33JC SL383

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 33MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 7-5.
Table 7-7.
Note:
14
FWH4/LFRAME
Clock Cycle
FWH/LAD[3:0]
13 - 14
3 - 10
11
12
15
16
17
18
19
1
2
1. Field contents are valid on the rising edge of the present clock cycle.
CLK
AT49LH004
LPC Read Cycle
LPC Read Cycle
CYCTYPE +
Field Name
0000b
START
MADDR
WSYNC
RSYNC
START
DATA
DATA
TAR0
TAR1
TAR0
TAR1
1
DIR
CYCTYPE
010xb
+ DIR
2
A31-A28
to the device to indicate that the master is turning control of the LPC bus over to the LPC
memory device. After the second clock of the TAR phase, the LPC device assumes control of
the bus and begins driving SYNC fields to add wait-states. When the device is ready to out-
put data, it will first send a “ready” SYNC and then output one byte of data during the next two
clock cycles. The data is sent one nibble at a time with the low nibble being output first fol-
lowed by the high nibble. After the data has been output, the LPC device will send a 2-clock
TAR field to the master to indicate that it is turning control of the LPC bus back over to the
master.
Figure 7-5
memory array.
3
FWH/LAD[3:0]
0000b (ready)
Field Value
1111b (float)
1111b (float)
0101b (wait)
A27-A24
0000b
010xb
1111b
1111b
YYYY
YYYY
YYYY
4
A23-A20 A19-A16
shows a LPC read cycle that requires three SYNC clocks to access data from the
5
(1)
MADDR
6
Float then OUT
FWH/LAD[3:0]
OUT then float
Float then IN
A15-A12
IN then float
Direction
7
OUT
OUT
OUT
OUT
IN
IN
IN
A11-A8
8
A7-A4
9
Comments
FWH4/LFRAME must be active (low) for the device to
respond. Only the last START field (before FWH4/LFRAME
transitioning high) should be recognized. The START field
contents indicate an LPC cycle.
Indicates that the cycle type is an LPC memory cycle and the
direction of the transfer is a read.
These eight clock cycles make up the 32-bit memory address.
YYYY is one nibble of the entire address. Addresses are
transferred with the most significant nibble first.
In this clock cycle, the master has driven the bus to all 1s and
then floats the bus prior to the next clock cycle. This is the first
part of the bus “turn-around cycle”.
The device takes control of the bus during this clock cycle.
The device outputs the value 0101b, a “wait” SYNC, for two
clock cycles. This value indicates to the master that data is not
yet available from the device. This number of wait-syncs is a
function of the device’s memory access time.
During this clock cycle, the device will generate a “ready”
SYNC indicating that the least significant nibble of the data
byte will be available during the next clock cycle.
YYYY is the least significant nibble of the data byte.
YYYY is the most significant nibble of the data byte.
The LPC memory device drives the bus to 1111b to indicate a
turn-around cycle.
The LPC memory device floats its outputs, and the master
regains control of the bus during this clock cycle.
A3-A0
10
1111b
TAR0
11
High-Z
TAR1
12
WSYNC
0101b
13
WSYNC
0101b
14
RSYNC
0000b
15
D3-D0
DATA
16
D7-D4
DATA
17
3383D–FLASH–6/05
1111b
TAR0
18
High-Z
TAR1
19