AT45DB021D-SSH-B Atmel, AT45DB021D-SSH-B Datasheet - Page 4

• Manufacturer Part Number: AT45DB021D-SSH-B
• Description: IC FLASH 2MBIT 66MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT45DB021D-SSH-B

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 2M (1024 pages x 264 bytes)
• Speed: 66MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Architecture: Sectored
• Interface Type: SPI
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 32 KB x 8
• Memory Configuration: 1024 Pages X 264 Bytes
• Clock Frequency: 66MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AT45DB021D-SSH; AT45DB021D-SSH; AT45DB021D-SSU; AT45DB021D-SSU

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3.
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Memory Array
To provide optimal flexibility, the memory array of the Atmel
granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the
breakdown of each level and details the number of pages per sector and block. All program operations to the Atmel
DataFlash
page level.
Figure 2-1.
Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions and their
associated opcodes are contained in
followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the CS pin
is low, toggling the SCK pin controls the loading of the opcode and the desired buffer or main memory address
location through the SI (serial input) pin. All instructions, addresses, and data are transferred with the most
significant bit (MSB) first.
Buffer addressing for the DataFlash standard page size (264-bytes) is referenced in the datasheet using the
terminology BFA8 - BFA0 to denote the nine address bits required to designate a byte address within a buffer.
Main memory addressing is referenced using the terminology PA9 - PA0 and BA8 - BA0, where PA9 - PA0
denotes the 10-address bits required to designate a page address and BA8 - BA0 denotes the nine address bits
required to designate a byte address within the page.
For the “Power of 2” binary page size (256-bytes), the Buffer addressing is referenced in the datasheet using the
conventional terminology BFA7 - BFA0 to denote the eight address bits required to designate a byte address within
a buffer. Main memory addressing is referenced using the terminology A17 - A0, where A17 - A8 denotes the 10-
address bits required to designate a page address and A7 - A0 denotes the eight address bits required to
designate a byte address within a page.
Atmel AT45DB021D
SECTOR ARCHITECTURE
SECTOR 1 = 128 Pages
SECTOR 6 = 128 Pages
SECTOR 0b = 120 Pages
SECTOR 7 = 128 Pages
SECTOR 0a = 8 Pages
32,768/33,792-bytes
32,768/33,792-bytes
32,768/33,792-bytes
31,744/32,726-bytes
2,048/2,112-bytes
®
occur on a page-by-page basis. The erase operations can be performed at the chip, sector, block or
Memory Architecture Diagram
SECTOR 0a
Tables 13-1 through
BLOCK ARCHITECTURE
Block = 1,024/1,056-bytes
BLOCK 126
BLOCK 127
BLOCK 14
BLOCK 15
BLOCK 16
BLOCK 17
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 0
BLOCK 1
BLOCK 2
13-7. A valid instruction starts with the falling edge of CS
®
AT45DB021D is divided into three levels of
8 Pages
PAGE ARCHITECTURE
Page = 256/264-bytes
PAGE 1,022
PAGE 1,023
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
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