AT45DB081D-MU-2.5 Atmel, AT45DB081D-MU-2.5 Datasheet - Page 4
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AT45DB081D-MU-2.5
Manufacturer Part Number
AT45DB081D-MU-2.5
Description
IC FLASH 8MBIT 50MHZ 8VDFN
Manufacturer
Atmel
Datasheet
1.AT45DB081D-MU.pdf
(53 pages)
Specifications of AT45DB081D-MU-2.5
Format - Memory
FLASH
Memory Type
DataFLASH
Memory Size
8M (4096 pages x 264 bytes)
Speed
50MHz
Interface
SPI, RapidS
Voltage - Supply
2.5 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-VFQFN, 8-VFQFPN
Architecture
Sectored
Interface Type
SPI
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
15 mA
Mounting Style
SMD/SMT
Organization
64 KB x 16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
3. Block Diagram
4. Memory Array
To provide optimal flexibility, the memory array of the Atmel
prising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and
details the number of pages per sector and block. All program operations to the Atmel DataFlash
basis. The erase operations can be performed at the chip, sector, block or page level.
Figure 4-1.
4
SECTOR ARCHITECTURE
RESET
Atmel AT45DB081D
SECTOR 14 = 256 Pages
SECTOR 15 = 256 Pages
SECTOR 1 = 256 Pages
SECTOR 2 = 256 Pages
SECTOR 0b = 248 Pages
GND
SECTOR 0a = 8 Pages
VCC
65,536-/67,584-bytes
65,536-/67,584-bytes
65,536-/67,584-bytes
SCK
65,536-/67,584-bytes
63,488-/65,472-bytes
2,048-/2,112-bytes
WP
CS
Memory Architecture Diagram
PAGE (256-/264-BYTES)
BUFFER 1 (256-/264-BYTES)
SECTOR 0a
SI
BLOCK ARCHITECTURE
Block = 2,048-/2,112-bytes
FLASH MEMORY ARRAY
I/O INTERFACE
BLOCK 510
BLOCK 511
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 0
BLOCK 1
BLOCK 2
®
AT45DB081D is divided into three levels of granularity com-
BUFFER 2 (256-/264-BYTES)
8 Pages
SO
PAGE ARCHITECTURE
®
occur on a page by page
Page = 256-/264-bytes
PAGE 4,094
PAGE 4,095
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
3596M–DFLASH–5/10