MT46H8M16LFCF-10 IT TR Micron Technology Inc, MT46H8M16LFCF-10 IT TR Datasheet - Page 8

• Manufacturer Part Number: MT46H8M16LFCF-10 IT TR
• Description: IC DDR SDRAM 128MBIT 60VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H8M16LFCF-10 IT TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 60-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
Initialization
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
1. It is recommended the core power (V
2. Once power supply voltages are stable and the CKE has been driven HIGH, it is safe to
3. Once the clock is stable, a 200µs minimum delay is required by the Mobile DDR
4. Issue a PRECHARGE ALL command.
5. Issue NOP or DESELECT commands for at least
6. Issue an AUTO REFRESH command followed by NOP or DESELECT commands for at
The 128Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access
memory containing 134,271,728-bits. It is internally configured as a quad-bank DRAM.
Each of the 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits.
The 128Mb Mobile DDR SDRAM uses a double data rate architecture to achieve high-
speed operation. The double data rate architecture is essentially a 2n-prefetch architec-
ture, with an interface designed to transfer two data words per clock cycle at the I/O
balls. single read or write access for the 128Mb Mobile DDR SDRAM consists of a single
2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corre-
sponding n-bit wide, one-half-clock-cycle data transfers at the I/O balls.
Read and write accesses to the Mobile DDR SDRAM are burst oriented; accesses start at
a selected location and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The address bits registered coin-
cident with the ACTIVE command are used to select the bank and row to be accessed
(BA0, BA1 select the bank; A0–A11 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the starting column location for
the burst access.
It should be noted that the DLL that is typically used on standard DDR devices is not
necessary on the Mobile DDR SDRAM. It has been omitted to save power.
Prior to normal operation, the Mobile DDR SDRAM must be initialized. The following
sections provide detailed information covering device initialization, register definition,
command descriptions and device operation.
Mobile DDR SDRAMs must be powered up and initialized in a predefined manner. Oper-
ational procedures other than those specified may result in undefined operation.
If there is an interruption to the device power, the initialization routine should be
followed to ensure proper functionality of the Mobile DDR SDRAM.
To properly initialize the Mobile DDR SDRAM, the following sequence must be followed:
power source and brought up simultaneously. If separate power sources are used, V
must lead V
apply the clock.
SDRAM prior to applying an executable command. During this time, NOP or DESE-
LECT commands must be issued on the command bus.
least
LECT commands for at least
AUTO REFRESH commands must be issued. Typically, both of these commands are
issued at this stage as described above. Alternately, the second AUTO-REFRESH com-
mand and NOP or DESELECT sequence can be issued after step 10.
t
RFC time. Issue a second AUTO REFRESH command followed by NOP or DESE-
DD
Q.
8
t
RFC time. As part of the individualization sequence, two
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
) and I/O power (V
t
RP time.
Functional Description
DD
©2004 Micron Technology, Inc. All rights reserved.
Q) be from the same
DD