IS42S16100C1-6T ISSI, Integrated Silicon Solution Inc, IS42S16100C1-6T Datasheet - Page 28
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IS42S16100C1-6T
Manufacturer Part Number
IS42S16100C1-6T
Description
IC SDRAM 16MBIT 166MHZ 50TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet
1.IS42S16100C1-7TL.pdf
(81 pages)
Specifications of IS42S16100C1-6T
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
16M (1M x 16)
Speed
166MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
50-TSOPII
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S16100C1-6TL
Manufacturer:
ISSI
Quantity:
1 000
28
IS42S16100C1
Interval Between Read Command
A new command can be executed while a read cycle is
in progress, i.e., before that cycle completes. When the
second read command is executed, after the CAS latency
has elapsed, data corresponding to the new read command
is output in place of the data due to the previous read
command.
CAS latency = 2, burstlength = 4
Interval Between Write Command
A new command can be executed while a write cycle is in
progress, i.e., before that cycle completes. At the point the
second write command is executed, data corresponding
to the new write command can be input in place of the
data for the previous write command.
CAS latency = 3, burstlength = 4
COMMAND
COMMAND
CLK
DQ
CLK
DQ
READ (CA=A, BANK 0) READ (CA=B, BANK 0)
WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0)
READ A0
WRITE A0 WRITE B0
D
IN
A0
READ B0
t
CCD
D
IN
t
CCD
B0
D
OUT
D
A0
IN
B1
D
OUT
The interval between two write commands (t
at least one clock cycle.
The selected bank must be set to the active state before
executing this command.
The interval between two read command (t
at least one clock cycle.
The selected bank must be set to the active state before
executing this command.
D
B0
IN
Integrated Silicon Solution, Inc. — www.issi.com
B2
D
OUT
D
B1
IN
B3
D
OUT
B2
D
OUT
B3
ccd
ccd
) must be
) must be
08/24/09
Rev. F