CY7C1339B-133AC Cypress Semiconductor Corp, CY7C1339B-133AC Datasheet - Page 4
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CY7C1339B-133AC
Manufacturer Part Number
CY7C1339B-133AC
Description
IC SRAM 4MBIT 133MHZ 100LQFP
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C1339B-100AC.pdf
(17 pages)
Specifications of CY7C1339B-133AC
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
4M (128K x 32)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3.15 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1093
Document #: 38-05141 Rev. *A
Pin Definitions
A
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
ZZ
DQ
V
V
V
V
MODE
NC
DNU
Pin Name
[16:0]
DD
SS
DDQ
SSQ
1
2
3
[31:0]
[3:0]
Asynchronous
Asynchronous
Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply.
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-Clock
I/O Ground
I/O Power
Ground
Supply
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Static
I/O-
I/O
–
-
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the
CLK if ADSP or ADSC is active LOW, and CE
two-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
Write is conducted (ALL bytes are written, regardless of the values on BW
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a Byte Write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
Output Enable, Asynchronous Input, active LOW. Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the first clock of a Read cycle when emerging from a deselected
state.
Advance Input Signal, sampled on the rising edge of CLK. When asserted, it automatically incre-
ments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A
is captured in the address registers. A
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A
is captured in the address registers. A
ADSC are both asserted, only ADSP is recognized.
ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition
with data integrity preserved. Leaving ZZ floating or NC will default the device into an active state.
ZZ has an internal pull down.
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by A
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ
in a three-state condition.
Ground for the core of the device. Should be connected to ground of the system.
Power supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power supply.
Ground for the I/O circuitry. Should be connected to ground of the system.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. When left floating or NC, defaults to interleaved burst order. Mode pin has an
internal pull up.
No Connects.
Do Not Use pins. These pins could be left floating or tied to GND.
2
1
1
[16:0]
and CE
and CE
and CE
during the previous clock rise of the Read cycle. The direction of the pins is controlled
2
3
3
to select/deselect the device.
to select/deselect the device. ADSP is ignored if CE
to select/deselect the device.
[1:0]
[1:0]
Pin Description
are also loaded into the burst counter. When ADSP and
are also loaded into the burst counter. When ADSP and
1
, CE
2
, and CE
3
are sampled active. A
1
is HIGH.
[3:0]
CY7C1339B
1
and BWE).
is deserted HIGH.
[31:0]
[1:0]
Page 4 of 17
DDQ
are placed
feed the
or left
[16:0]
[16:0]