CY7C1361A-100AC Cypress Semiconductor Corp, CY7C1361A-100AC Datasheet - Page 5

• Manufacturer Part Number: CY7C1361A-100AC
• Description: IC SRAM 9MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1361A-100AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1117

Document #: 38-05259 Rev. *C
256K × 36 Pin Descriptions
2A, 3A, 5A, 6A, 3B, 5B,
6B, 2C, 3C, 5C, 6C,
2R, 6R, 3T, 4T, 5T
X36 PBGA Pins
(not available for
PBGA)
4N
5G
3G
4M
4H
4G
3R
4P
4K
4E
2B
4F
4A
4B
7T
5L
3L
–
35, 34, 33, 32, 100,
(for A version only)
99, 82, 81, 44, 45,
46, 47, 48, 49, 50
92 (AJ Version)
X36 QFP Pins
43 (A Version)
37
36
93
94
95
96
87
88
89
98
97
92
86
83
84
85
31
64
MODE
Name
ADSP
ADSC
BWb
BWd
BWE
BWa
BWc
ADV
CLK
CE
CE
GW
Pin
CE
OE
A0
A1
ZZ
A
2
2
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Static
Type
Input
Addresses: These inputs are registered and must meet
the set-up and hold times around the rising edge of CLK.
The burst counter generates internal addresses
associated with A0 and A1, during burst cycle and wait
cycle.
Byte Write: A byte Write is LOW for a Write cycle and
HIGH for a Read cycle. BWa controls DQa. BWb controls
DQb. BWc controls DQc. BWd controls DQd. Data I/O are
high impedance if either of these inputs are LOW, condi-
tioned by BWE being LOW.
Write Enable: This active LOW input gates byte Write
operations and must meet the set-up and hold times
around the rising edge of CLK.
Global Write: This active LOW input allows a full 36-bit
Write to occur independent of the BWE and BWn lines
and must meet the set-up and hold times around the rising
edge of CLK.
Clock: This signal registers the addresses, data, chip
enables, Write control, and burst control inputs on its
rising edge. All synchronous inputs must meet set-up and
hold times around the clock’s rising edge.
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP.
Chip Enable: This active HIGH input is used to enable
the device.
Chip Enable: This active LOW input is used to enable the
device. Not available for BG and AJ package versions.
Output Enable: This active LOW asynchronous input
enables the data output drivers.
Address Advance: This active LOW input is used to
control the internal burst counter. A HIGH on this pin
generates wait cycle (no address advance).
Address Status Processor: This active LOW input,
along with CE being LOW, causes a new external address
to be registered and a Read cycle is initiated using the
new address.
Address Status Controller: This active LOW input
causes the device to be deselected or selected along with
new external address to be registered. A Read or Write
cycle is initiated depending upon Write control inputs.
Mode: This input selects the burst sequence. A LOW on
this pin selects Linear Burst. A NC or HIGH on this pin
selects Interleaved Burst.
Sleep: This active HIGH input puts the device in
low-power consumption standby mode. For normal
operation, this input has to be either LOW or NC (No
Connect).
Pin Description
CY7C1361A
CY7C1363A
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