CY7C1361A-100AC Cypress Semiconductor Corp, CY7C1361A-100AC Datasheet - Page 8

• Manufacturer Part Number: CY7C1361A-100AC
• Description: IC SRAM 9MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1361A-100AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1117

Document #: 38-05259 Rev. *C
Truth Table
Burst Address Table (MODE = NC/V
Notes:
Deselected Cycle, Power-down None
Deselected Cycle, Power-down None
Deselected Cycle, Power-down None
Deselected Cycle, Power-down None
Deselected Cycle, Power-down None
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
3.
4.
5.
6.
7.
8.
9.
(external)
Address
A...A00
A...A01
A...A10
A...A11
X = “Don’t Care.” H = logic HIGH. L = logic LOW.
For X36 product, Write = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. Write = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.
For X18 product, Write = L means [BWE + BWa*BWb]*GW equals LOW. Write = H means [BWE + BWa*BWb]*GW equals HIGH.
BWa enables Write to DQa. BWb enables Write to DQb. BWc enables Write to DQc. BWd enables Write to DQd.
All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
Suspending burst generates wait cycle.l
For a Write operation following a Read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A Write cycle can be performed by setting Write LOW for the
CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
First
Operation
[3, 4, 5, 6, 7, 8, 9]
(internal)
Address
Second
A...A01
A...A00
A...A10
A...A11
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
(internal)
Address Used CE CE2 CE2 ADSP ADSC ADV
Address
A...A10
A...A00
A...A01
A...A11
Third
CC
(internal)
Address
)
A...A10
A...A01
A...A00
Fourth
A...A11
H
H
H
H
H
H
H
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
H
H
X
X
X
X
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
Burst Address Table (MODE = GND)
(external)
Address
A...A00
A...A01
A...A10
A...A11
First
H
H
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
X
L
L
L
L
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
(internal)
Address
Second
A...A01
A...A10
A...A00
A...A11
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
L
L
L
L
L
L
Write
H
H
H
H
H
H
X
X
X
X
X
X
X
H
H
H
H
L
L
L
L
L
(internal)
Address
A...A10
A...A11
A...A00
A...A01
Third
OE
X
X
X
X
X
H
X
H
H
H
X
X
H
H
X
X
L
L
L
L
L
L
CY7C1361A
CY7C1363A
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Page 8 of 27
(internal)
Address
A...A00
A...A01
A...A10
Fourth
A...A11
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DQ
Q
Q
Q
Q
Q
Q
D
D
D
D
D