CY7C008V-15AC Cypress Semiconductor Corp, CY7C008V-15AC Datasheet

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CY7C008V-15AC

Manufacturer Part Number
CY7C008V-15AC
Description
IC SRAM 512KBIT 15NS 100LQFP
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C008V-15AC

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
512K (64K x 8)
Speed
15ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1147

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C008V-15AC
Manufacturer:
CY
Quantity:
14
Part Number:
CY7C008V-15AC
Manufacturer:
TI
Quantity:
227
Part Number:
CY7C008V-15AC
Manufacturer:
CYPRESS
Quantity:
210
Part Number:
CY7C008V-15AC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Cypress Semiconductor Corporation
Document #: 38-06044 Rev. *B
Features
Notes:
1.
2.
3.
• True Dual-Ported memory cells which allow simulta-
• 64K x 8 organization (CY7C008)
• 128K x 8 organization (CY7C009)
• 64K x 9 organization (CY7C018)
• 128K x 9 organization (CY7C019)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 15/20/25 ns
• Low operating power
Logic Block Diagram
A
A
CE
OE
R/W
SEM
BUSY
INT
R/W
CE
CE
OE
I/O
neous access of the same memory location
— Active: I
— Standby: I
0L
0L
I/O
A
BUSY is an output in master mode and an input in slave mode.
L
0
L
0L
0L
1L
L
–A
–A
L
–A
0
L
L
L
–I/O
–I/O
15
[2]
[2]
L
15/16L
15/16L
[3]
for 64K devices; A
7
7/8L
for x8 devices; I/O
[1]
CC
SB3
= 115 mA (typical)
CE
= 10 A (typical)
16/17
L
For the most recent information, visit the Cypress web site at www.cypress.com
8/9
0
–A
0
–I/O
16
for 128K.
8
for x9 devices.
Address
Decode
16/17
3901 North First Street
Control
I/O
True Dual-Ported
Semaphore
RAM Array
Arbitration
Interrupt
M/S
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 16/18 bits or more using Mas-
• On-chip arbitration logic
• Semaphores included to permit software handshaking
• INT flag for port-to-port communication
• Dual Chip Enables
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Available in 100-pin TQFP
ter/Slave chip select when using more than one device
between ports
Control
I/O
San Jose
Dual-Port Static RAM
3.3V 64K/128K x 8/9
Address
Decode
16/17
CA 95134
CY7C008V/009V
CY7C018V/019V
Revised December 27, 2002
16/17
8/9
CE
R
I/O
A
A
408-943-2600
[3]
0R
0R
0R
–A
–A
–I/O
[2]
[2]
BUSY
SEM
R/W
15/16R
15/16R
CE
CE
R/W
[1]
INT
OE
OE
CE
7/8R
0R
1R
R
R
R
R
R
R
R
R

Related parts for CY7C008V-15AC

CY7C008V-15AC Summary of contents

Page 1

... Commercial and Industrial Temperature Ranges • Available in 100-pin TQFP I/O I/O Control Control True Dual-Ported RAM Array Interrupt Semaphore Arbitration M/S • 3901 North First Street • San Jose CY7C008V/009V CY7C018V/019V 3.3V 64K/128K x 8/9 Dual-Port Static RAM R [1] 8/9 I/O –I/O 0R 7/8R ...

Page 2

... Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select (CE) pin. The CY7C008V/009V and CY7018V/019V are available in 100-pin Thin Quad Plastic Flatpacks (TQFP). 100-Pin TQFP (Top View) ...

Page 3

... TQFP (Top View CY7C019V (128K x 9) CY7C018V (64K CY7C008V/009V CY7C018V/019V -15 15 125 CY7C008V/009V CY7C018V/019V A7R 72 A8R 71 A9R 70 A10R 69 A11R 68 A12R 67 A13R 66 A14R 65 A15R 64 A16R 63 GND CE0R 57 CE1R 56 SEMR 55 R/WR 54 OER 53 GND 52 GND CY7C008V/009V CY7C008V/009V CY7C018V/019V CY7C018V/019V -20 20 120 [5] -25 25 115 Page ...

Page 4

... Interrupt Flag Busy Flag Master or Slave Select Power Ground No Connect DC Input Voltage ..................................... –0. Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >1100V Latch-Up Current.................................................... >200 mA Operating Range Range Commercial +0.5V CC Industrial CY7C008V/009V CY7C018V/019V Description V and –A for 128K devices –I/O for x8 devices and I/O – ...

Page 5

... Test Conditions MHz 3. 250 TH OUTPUT C = 30pF (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0V 90% 10% GND 3 ns CY7C008V/009V CY7C018V/019V CY7C008V/009V CY7C018V/019V -20 -25 Max. Min. Typ. Max. Min. Typ. Max. 2.4 2.4 0.4 0.4 2.2 2.2 0.8 0.8 5 –5 5 –5 10 –10 10 –10 ...

Page 6

... For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 16. Test conditions used are Load 1. 17 calculated parameter and is the greater of t BDD Document #: 38-06044 Rev. *B [10] -15 Min. Max less than t and t HZCE LZCE –t (actual –t (actual). WDD PWE DDD SD CY7C008V/009V CY7C018V/019V CY7C008V/009V CY7C018V/019V -20 -25 Min. Max. Min. Max ...

Page 7

... SEM Address Access Time SAA Data Retention Mode The CY7C008V/009V and CY7018V/019V are designed with battery backup in mind. Data retention voltage and supply cur- rent are guaranteed over temperature. The following rules en- sure data retention: 1. Chip enable (CE) must be held HIGH during data retention, with- ...

Page 8

... To access RAM SEM = access semaphore Document #: 38-06044 Rev. *B [19, 20, 21 [19, 22, 23] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE . This waveform cannot be used for semaphore reads. , SEM = CY7C008V/009V CY7C018V/019V t OHA DATA VALID t HZCE t HZOE DATA VALID OHA t HZCE Page ...

Page 9

... If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. Document #: 38-06044 Rev. *B [24, 25, 26, 27 [27] t PWE [29] t HZWE t SD [24, 25, 26, 31 SCE LOW CE or SEM. PWE or (t PWE CY7C008V/009V CY7C018V/019V [29] t HZOE LZWE NOTE allow the I/O drivers to turn off and data to be placed on HZWE SD . PWE Page ...

Page 10

... SPS Document #: 38-06044 Rev. *B [32 SCE t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE [33, 34, 35] MATCH t SPS MATCH = CE = HIGH CY7C008V/009V CY7C018V/019V t t SAA OHA VALID ADRESS t ACE t SOP DATA VALID OUT t DOE READ CYCLE Page ...

Page 11

... Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 36 LOW Document #: 38-06044 Rev. *B [36 MATCH t PWE t SD VALID MATCH t BLA t PWE CY7C008V/009V CY7C018V/019V BHA t BDD t DDD VALID t WDD Page ...

Page 12

... BUSY will be asserted. PS Document #: 38-06044 Rev. *B [37] ADDRESS MATCH BLC ADDRESS MATCH BLC [37 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C008V/009V CY7C018V/019V t BHC t BHC Page ...

Page 13

... Notes: 38. t depends on which enable pin ( depends on which enable pin (CE INS INR Document #: 38-06044 Rev [38 [39] t INR t WC [38 [39] [39] t INR ) is deasserted first R asserted last CY7C008V/009V CY7C018V/019V t RC READ FFFF (1FFFF for CY7C009V/19V READ 1FFE (1FFFF for CY7C009V/19V) Page ...

Page 14

... Architecture The CY7C008V/009V and CY7018V/019V consist of an array of 64K and 128K words of 8 and 9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port ...

Page 15

... No change. Left port has no write access to semaphore 0 1 Left port obtains semaphore token 1 1 Semaphore free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C008V/009V CY7C018V/019V Operation [40] Right Port R 0R–16R ...

Page 16

... Ordering Information 64K x8 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C008V-15AC 20 CY7C008V-20AC 25 CY7C008V-25AC 64K x9 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C018V-15AC 20 CY7C018V-20AC 25 CY7C018V-25AC 128K x8 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C009V-15AC 20 CY7C009V-20AC CY7C009V-20AI 25 CY7C009V-25AC 128K x9 3.3V Asynchronous Dual-Port SRAM ...

Page 17

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C008V/009V CY7C018V/019V ...

Page 18

... Document Title: CY7C008V/009V, CY7C018V/019V 3.3V 64K/128K X 8/9 Dual Port Static RAM Document Number: 38-06044 Issue REV. ECN NO. Date ** 110192 09/29/01 *A 113541 04/15/02 *B 122294 12/27/02 Document #: 38-06044 Rev. *B Orig. of Change Description of Change SZV Change from Spec number: 38-00669 to 38-06044 OOR Change pin 85 from BUSYL to BUSYR (pg. 3) ...

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