M25P10-AVMN6T STMicroelectronics, M25P10-AVMN6T Datasheet - Page 12
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M25P10-AVMN6T
Manufacturer Part Number
M25P10-AVMN6T
Description
IC FLASH 1MBIT 40MHZ 8SOIC
Manufacturer
STMicroelectronics
Datasheet
1.M25P10-AVMP6T.pdf
(51 pages)
Specifications of M25P10-AVMN6T
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
1M (128K x 8)
Speed
50MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
497-1622-2
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Operating features
4.5
4.6
12/51
Status Register
The Status Register contains a number of status and control bits, as shown in
can be read or set (as appropriate) by specific instructions. For a detailed description of the
Status Register bits, see
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P10-A features the following data protection mechanisms:
Power On Reset and an internal timer (t
changes while the power supply is outside the operating specification.
Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
–
–
The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-
only. This is the Software Protected mode (SPM).
The Write Protect (W) signal, in co-operation with the Status Register Write Disable
(SRWD) bit, allows the Block Protect (BP1, BP0) bits and Status Register Write Disable
(SRWD) bit to be write-protected. This is the Hardware Protected mode (HPM).
In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection, as all write, program and erase instructions are ignored.
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Section 6.4: Read Status Register
PUW
) can provide protection against inadvertent
(RDSR).
Table
M25P10-A
6, that