PSD4235G2V-12UI STMicroelectronics, PSD4235G2V-12UI Datasheet - Page 61

• Manufacturer Part Number: PSD4235G2V-12UI
• Description: IC FLASH 4MBIT 120NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD4235G2V-12UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Number Of Macrocells: 24
• Maximum Operating Frequency: 25.6 MHz
• Delay Time: 90 ns
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1970

PSD4235G2
18
Complex PLD (CPLD)
The CPLD can be used to implement system logic functions, such as loadable counters and
shift registers, system mailboxes, handshaking protocols, state machines, and random logic.
The CPLD can also be used to generate eight External Chip Select (ECS0-ECS7), routed to
Port C or Port F.
Although External Chip Select (ECS0-ECS7) can be produced by any output macrocell
(OMC), these eight External Chip Select (ECS0-ECS7) on Port C or Port F do not consume
any output macrocells (OMC).
As shown in
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Each of the blocks are described in the sections that follow.
The input macrocells (IMC) and output macrocells (OMC) are connected to the PSD internal
data bus and can be directly accessed by the MCU. This enables the MCU software to load
data into the output macrocells (OMC) or read data from both the input and output
macrocells (IMC and OMC).
This feature allows efficient implementation of system logic and eliminates the need to
connect the data bus to the AND Array as required in most standard PLD macrocell
architectures.
24 input macrocells (IMC)
16 output macrocells (OMC)
Product Term Allocator
AND Array capable of generating up to 196 product terms
Four I/O Ports.
Figure
11, the CPLD has the following blocks:
Complex PLD (CPLD)
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