PSD4235G2V-12UI STMicroelectronics, PSD4235G2V-12UI Datasheet - Page 95

• Manufacturer Part Number: PSD4235G2V-12UI
• Description: IC FLASH 4MBIT 120NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD4235G2V-12UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Number Of Macrocells: 24
• Maximum Operating Frequency: 25.6 MHz
• Delay Time: 90 ns
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1970

PSD4235G2
21.1
21.2
Automatic Power-down (APD) Unit and Power-down mode
The APD Unit, shown in
activity of Address Strobe (ALE/AS, PD0). If the APD Unit is enabled, as soon as activity on
Address Strobe (ALE/AS, PD0) stops, a four-bit counter starts counting. If Address Strobe
(ALE/AS, PD0) remains inactive for fifteen clock periods of CLKIN (PD1), Power-down
(PDN) goes high, and the PSD enters Power-down mode, as discussed next.
Power-down mode
By default, if you enable the APD Unit, Power-down mode is automatically enabled. The
device enters Power-down mode if Address Strobe (ALE/AS, PD0) remains inactive for
fifteen periods of CLKIN (PD1).
The following should be kept in mind when the PSD is in Power-down mode:
●
●
●
●
●
Table 48.
MCU I/O
PLD Out
Address Out
Data port
Peripheral I/O
If Address Strobe (ALE/AS, PD0) starts pulsing again, the PSD returns to normal
operation. The PSD also returns to normal operation if either PSD Chip Select input
(CSI, PD2) is low or the Reset (RESET) input is high.
The MCU address/data bus is blocked from all memory and PLDs.
Various signals can be blocked (prior to Power-down mode) from entering the PLDs by
setting the appropriate bits in the Power Management Mode registers (PMMR). The
blocked signals include MCU control signals and the common CLKIN (PD1). Note that
blocking CLKIN (PD1) from the PLDs does not block CLKIN (PD1) from the APD Unit.
All PSD memories enter Standby mode and are drawing standby current. However, the
PLDs and I/O ports blocks do not go into Standby mode because you do not want to
have to wait for the logic and I/O to “wakeup” before their outputs can change. See
Table 48
Typical standby current is or the order of µA. This standby current value assumes that
there are no transitions on any PLD input.
Effect of Power-down mode on ports
for Power-down mode effects on PSD ports.
Port function
Figure
31, puts the PSD into Power-down mode by monitoring the
No Change
No Change
Undefined
Pin level
Tri-State
Tri-State
Power management
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