CY7C1325F-100AC Cypress Semiconductor Corp, CY7C1325F-100AC Datasheet
CY7C1325F-100AC
Specifications of CY7C1325F-100AC
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CY7C1325F-100AC Summary of contents
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... Asynchronous output enable • Offered in JEDEC-standard 100-pin TQFP and 119-ball BGA packages • “ZZ” Sleep Mode option [1] Functional Description The CY7C1325F is a 262,144 x 18 synchronous cache RAM designed to interface with high-speed microprocessors with Logic Block Diagram ADDRESS A0,A1,A REGISTER ...
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... Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Pin Configurations DDQ DDQ BYTE DDQ DQP DDQ Document #: 38-05215 Rev. *B 133 MHz 117 MHz 6.5 7.5 225 220 40 40 100-Pin TQFP CY7C1325F CY7C1325F 100 MHz 66 MHz Unit 8.0 11.0 205 195 DDQ DQP DDQ BYTE DDQ DDQ Page ...
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... Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Synchronous Used in conjunction with CE ADSP is ignored if CE Input- Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Synchronous Used in conjunction with CE Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Synchronous Used in conjunction with CE CY7C1325F DDQ ...
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... When tied left floating selects interleaved burst sequence. DD This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. No Connects. Not Internally connected to the die. CY7C1325F Description are also loaded into [1:0] is deasserted HIGH 1 are also loaded into ...
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... Maximum access delay from the clock rise ( 6.5 ns (133-MHz device). C0 The CY7C1325F supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium processors. The linear burst sequence is suited for processors that utilize a linear burst sequence ...
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... and BWE = L or GW= L. WRITE = H when all Byte write enable signals ( CY7C1325F Min. Max. Unit CYC 2t ns CYC 2t ns CYC 0 ns ADV WRITE OE CLK L-H three-state L-H three-state L-H three-state L-H three-state L-H three-state three-state L L-H three-state L L L-H three-state L-H Q ...
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... Truth Table for Read/Write [2] Function Read Read Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ) B B Write All Bytes Write All Bytes Document #: 38-05215 Rev BWE CY7C1325F Page ...
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... V – 0. inputs static /2), undershoot: V (AC) > -2V (Pulse width less than t CYC IL (min.) within 200ms. During this time V < CY7C1325F Ambient ] Temperature V DD 3.3V −5%/+10% 2.5V –5% 0°C to +70°C –40°C to +85°C CY7C1345F Min. 3.135 2.375 = –4.0 mA 2.4 = – ...
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... R = 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V OUTPUT =1538Ω INCLUDING JIG AND (b) SCOPE CY7C1325F CY7C1345F Min. Max. 7.5-ns cycle, 133 MHz 8.0-ns cycle, 117 MHz 10-ns cycle, 100 MHz 15-ns cycle, 66 MHz All speeds TQFP BGA Package. Package 41.83 47 ...
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... V POWER is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 3.3V and is 1.25V when V = 2.5V. DDQ CY7C1325F 117 MHz 100 MHz 66 MHz 8 3.0 4.0 5 ...
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... WEH t t ADVS ADVH t CDV t OELZ t OEHZ t DOH Q(A2) Q( DON’T CARE is HIGH and CE is LOW. When CE is HIGH [A:B] CY7C1325F ADV suspends burst Q( Q( Q(A2) Q( Burst wraps around to its initial state BURST READ UNDEFINED is HIGH LOW HIGH LOW. Deselect Cycle ...
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... D(A1) t OEHZ Data Out (Q) BURST READ Single WRITE Document #: 38-05215 Rev. *B ADSC extends burst WES WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED CY7C1325F t ADS t ADH A3 t WES t WEH t ADVS t ADVH D( D(A3 Extended BURST WRITE Page ...
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... The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC . 19 HIGH. Document #: 38-05215 Rev WES WEH OELZ D(A3) t OEHZ t CDV Q(A4) Single WRITE DON’T CARE CY7C1325F A5 D(A5) Q(A4+1) Q(A4+2) Q(A4+3) Back-to-Back BURST READ WRITEs UNDEFINED A6 D(A6) Page ...
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... Ordering Code 133 CY7C1325F-133AC CY7C1325F-133BGC CY7C1325F-133AI CY7C1325F-133BGI 117 CY7C1325F-117AC CY7C1325F-117BGC CY7C1325F-117AI CY7C1325F-117BGI 100 CY7C1325F-100AC CY7C1325F-100BGC CY7C1325F-100AI CY7C1325F-100BGI 66 CY7C1325F-66AC CY7C1325F-66BGC CY7C1325F-66AI CY7C1325F-66BGI Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05215 Rev ...
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... Package Diagram 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05215 Rev. *B CY7C1325F 51-85050-*A Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 119-Lead BGA ( 2.4 mm) BG119 CY7C1325F 51-85115-*B Page ...
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... Document Title: CY7C1325B 4-Mb (256K x 18) Flow-Through Sync SRAM Document Number: 38-05215 REV. ECN NO. Issue Date ** 119834 01/06/03 *A 123848 01/18/03 *B 200663 12/19/03 Document #: 38-05215 Rev. *B Orig. of Change HGK New Data Sheet AJH Added power-up requirements to AC test loads and waveforms information SWI Final Data Sheet CY7C1325F Description of Change Page ...