CY7C1327F-133AC Cypress Semiconductor Corp, CY7C1327F-133AC Datasheet - Page 4

• Manufacturer Part Number: CY7C1327F-133AC
• Description: IC SRAM 4.5MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1327F-133AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4.5M (256K x 18)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1536

Document #: 38-05216 Rev. *B
Pin Definitions
A
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
ADSP
ZZ
ADSC
DQ
DQ
DQP
DQP
0
, A
Name
1
2
3
A,
B
A,
A,
B
1
BW
, A
B
8,9,12,13,
32,33,34,
35,44,45,
46,47,48,
49,50,80,
81,82,99,
58,59,62,
63,68,69,
18,19,22,
37,36,
TQFP
93,94
72,73
74,24
100
88
87
89
98
97
92
86
83
84
64
85
23
N6,E7,G7,
N1,E2,G2,
P4,N4,A2,
C2,R2,T2,
A3,B3,C3,
T3,A5,B5,
C5,T5,A6,
F6,H6,L6,
D1,H1,L1,
C6,R6,T6
K2,M2,
L5,G3
K7,P7
D6,P2
BGA
M4
G4
H4
K4
E4
B2
B6
A4
B4
F4
T7
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-
Input-
Input-
Input-
Input-
Clock
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
I/O-
I/O
Address Inputs used to select one of the 256K address locations. Sampled
at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE
CE
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct
byte writes to the SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the
rising edge of CLK, a global write is conducted (ALL bytes are written,
regardless of the values on BW
Byte Write Enable Input, active LOW. Sampled on the rising edge of
CLK. This signal must be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also
used to increment the burst counter when ADV is asserted LOW, during
a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK.
Used in conjunction with CE
is ignored if CE
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK.
Used in conjunction with CE
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK.
Used in conjunction with CE
connected for BGA. Where referenced, CE
this document for BGA.
Output Enable, asynchronous input, active LOW. Controls the
direction of the I/O pins. When LOW, the I/O pins behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act as input data pins.
OE is masked during the first clock of a read cycle when emerging from a
deselected state.
Advance Input signal, sampled on the rising edge of CLK, active
LOW. When asserted, it automatically increments the address in a burst
cycle.
Address Strobe from Processor, sampled on the rising edge of CLK,
active LOW. When asserted LOW, A is captured in the address registers.
A1, A0 are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized. ASDP is ignored when CE
deasserted HIGH.
ZZ “sleep” Input, active HIGH. This input, when High places the device
in a non-time-critical “sleep” condition with data integrity preserved. For
normal operation, this pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
Address Strobe from Controller, sampled on the rising edge of CLK,
active LOW. When asserted LOW, A is captured in the address registers.
A1, A0 are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data
register that is triggered by the rising edge of CLK. As outputs, they deliver
the data contained in the memory location specified by “A” during the
previous clock rise of the read cycle. The direction of the pins is controlled
by OE . When OE is asserted LOW, the pins behave as outputs. When
HIGH, DQs and DQP
2
, and CE
3
are sampled active. A1, A0 feed the 2-bit counter.
1
is HIGH.
[A:B]
are placed in a three-state condition.
2
1
1
and CE
and CE
and CE
Description
[A:B]
3
and BWE).
2
to select/deselect the device. ADSP
3
to select/deselect the device. Not
to select/deselect the device.
3
is assumed active throughout
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