CY7C1471V33-117AXC Cypress Semiconductor Corp, CY7C1471V33-117AXC Datasheet - Page 21

• Manufacturer Part Number: CY7C1471V33-117AXC
• Description: IC SRAM 72MBIT 117MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1471V33-117AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 117MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-05288 Rev. *I
Switching Characteristics
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Set-up Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Notes:
17. This part has a voltage regulator internally; t
18. t
19. At any given voltage and temperature, t
20. This parameter is sampled and not 100% tested.
21. Timing reference level is 1.5V when V
22. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
POWER‘
CYC
CH
CL
CDV
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ALS
WES
CENS
DS
CES
AH
ALH
WEH
CENH
DH
CEH
Parameter
can be initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
CHZ
, t
CLZ
,t
OELZ
, and t
OEHZ
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
Clock Cycle Time
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z
Clock to High-Z
OE LOW to Output Valid
OE LOW to Output Low-Z
OE HIGH to Output High-Z
Address Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise
WE, BW
CEN Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
Address Hold After CLK Rise
ADV/LD Hold After CLK Rise
WE, BW
CEN Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
DDQ
OEHZ
Over the Operating Range
X
X
= 3.3V and is 1.25V when V
POWER
Set-up Before CLK Rise
Hold After CLK Rise
is less than t
is the time that the power needs to be supplied above V
[18, 19, 20]
[18, 19, 20]
Description
OELZ
and t
[18, 19, 20]
[18, 19, 20]
CHZ
DDQ
is less than t
[21, 22]
= 2.5V.
CLZ
to eliminate bus contention between SRAMs when sharing the same
Min.
7.5
2.5
2.5
2.5
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
0
133 MHz
DD
(minimum) initially, before a Read or Write operation
Max.
6.5
3.8
3.0
3.0
Min.
3.0
3.0
2.5
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
10
1
0
117 MHz
CY7C1471V33
CY7C1473V33
CY7C1475V33
Max.
8.5
4.5
3.8
4.0
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Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns