M45PE80-VMP6 NUMONYX, M45PE80-VMP6 Datasheet - Page 24

• Manufacturer Part Number: M45PE80-VMP6
• Description: IC FLASH 8MBIT 25MHZ 8VFQFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M45PE80-VMP6

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 25MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M45PE80
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must
not be selected (that is Chip Select (S) must follow
the voltage applied on V
correct value:
–
–
Usually a simple pull-up resistor on Chip Select (S)
can be used to insure safe and proper Power-up
and Power-down.
To avoid data corruption and inadvertent write op-
erations during power up, a Power On Reset
(POR) circuit is included. The logic inside the de-
vice is held reset while V
threshold value, V
and the device does not respond to any instruc-
tion.
Moreover, the device ignores all Write Enable
(WREN), Page Write (PW), Page Program (PP),
Page Erase (PE) and Sector Erase (SE) instruc-
tions until a time delay of t
the moment that V
old. However, the correct operation of the device
is not guaranteed if, by this time, V
V
should be sent until the later of:
Figure 20. Power-up Timing
24/36
CC
V
delay of t
V
(min). No Write, Program or Erase instructions
V CC (max)
CC
SS
V CC (min)
(min) at Power-up, and then for a further
at Power-down
V WI
V CC
VSL
Reset State
Device
of the
WI
CC
– all operations are disabled,
Program, Erase and Write Commands are Rejected by the Device
rises above the V
CC
CC
Chip Selection Not Allowed
) until V
PUW
is less than the POR
has elapsed after
CC
CC
is still below
reaches the
WI
thresh-
tPUW
tVSL
–
–
These values are specified in
If the delay, t
above V
READ instructions even if the t
fully elapsed.
As an extra protection, the Reset (Reset) signal
could be driven Low for the whole duration of the
Power-up and Power-down phases.
At Power-up, the device is in the following state:
–
–
Normal precautions must be taken for supply rail
decoupling, to stablise the V
in a system should have the V
a suitable capacitor close to the package pins.
(Generally, this capacitor is of the order of 0.1µF).
At Power-down, when V
ing voltage, to below the POR threshold value,
V
does not respond to any instruction. (The designer
needs to be aware that if a Power-down occurs
while a Write, Program or Erase cycle is in
progress, some data corruption can result.)
WI
Read Access allowed
, all operations are disabled and the device
t
t
The device is in the Standby mode (not the
Deep Power-down mode).
The Write Enable Latch (WEL) bit is reset.
PUW
VSL
CC
after V
after V
(min), the device can be selected for
VSL
CC
CC
, has elapsed, after V
passed the V
passed the V
Device fully
accessible
CC
drops from the operat-
CC
CC
Table
PUW
feed. Each device
CC
time
WI
rail decoupled by
(min) level
delay is not yet
threshold
6..
CC
AI04009C
has risen