CY7C1568V18-400BZXCT Cypress Semiconductor Corp, CY7C1568V18-400BZXCT Datasheet - Page 6

• Manufacturer Part Number: CY7C1568V18-400BZXCT
• Description: IC SRAM 72MBIT 400MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1568V18-400BZXCT

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 72M (2M x 36)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Definitions
Document Number: 001-06551 Rev. *E
DQ
LD
NWS
NWS
BWS
BWS
BWS
BWS
A
R/W
QVLD
K
K
CQ
CQ
Pin Name
[x:0]
0
1
2
3
0
1
,
,
,
,
Input
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
Valid Output
Input Clock
Input Clock
Input and
Indicator
Output
Input
Input
Input
Input
IO
Data Input and Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid
write operations. These pins drive out the requested data during a read operation. Valid data is driven out
on the rising edge of both the K and K clocks during read operations. When read access is deselected,
Q
CY7C1566V18 − DQ
CY7C1577V18 − DQ
CY7C1568V18 − DQ
CY7C1570V18 − DQ
Synchronous Load. Sampled on the rising edge of the K clock. This input is brought LOW when a bus
cycle sequence is defined. This definition includes address and read or write direction. All transactions
operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.
Nibble Write Select 0, 1 − Active LOW (CY7C1566V18 only). Sampled on the rising edge of the K and
K clocks during write operations. Used to select the nibble that is written into the device during the current
portion of the write operations. Nibbles not written remain unaltered.
NWS
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and does not write into the device.
Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1577V18 − BWS
CY7C1568V18 − BWS
CY7C1570V18 − BWS
BWS
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and does not write into the device.
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
address inputs are multiplexed for both read and write operations. Internally, the device is organized as
8M x 8 (2 arrays each of 4M x 8) for CY7C1566V18, 8M x 9 (2 arrays each of 4M x 9) for CY7C1577V18,
4M x 18 (2 arrays each of 2M x 18) for CY7C1568V18, and 2M x 36 (2 arrays each of 1M x 36) for
CY7C1570V18.
Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read when
R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times
around edge of K.
Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
edge of K.
Negative Input Clock Input. K is used to capture synchronous data presented to the device and to drive
out data through Q
(K) of the DDR-II+. The timing for the echo clocks is shown in
(K) of the DDR-II+. The timing for the echo clocks is shown in
[x:0]
2
0
are automatically tri-stated.
controls D
controls D
[26:18]
[3:0]
[x:0]
[7:0]
[8:0]
[17:0]
[35:0]
and NWS
0
0
0
when in single clock mode.
and BWS
controls D
controls D
controls D
1
[x:0]
controls D
3
controls D
[8:0]
[8:0]
[8:0]
when in single clock mode. All accesses are initiated on the rising
, BWS
and BWS
[7:4]
Pin Description
1
[35:27]
.
controls D
1
controls D
.
CY7C1566V18, CY7C1577V18
CY7C1568V18, CY7C1570V18
[17:9]
[17:9].
,
Switching Characteristics
Switching Characteristics
on page 23.
on page 23.
Page 6 of 28
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