NAND01GW3B2BZA6E NUMONYX, NAND01GW3B2BZA6E Datasheet
NAND01GW3B2BZA6E
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NAND01GW3B2BZA6E Summary of contents
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... RoHS compliant packages Development tools – Error correction code models – Bad blocks management and wear leveling – Hardware simulation models NAND01GR3B2C, NAND01GW3B2C NAND01GR4B2C, NAND01GW4B2C Rev 5 TSOP48 FBGA VFBGA63 1.05 mm VFBGA153 x0.9 mm power transitions (with ECC) algorithms Root part numbers (1) 1/67 www.numonyx.com 1 ...
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... Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 Bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 Inputs/outputs (I/O0-I/O7 3.2 Inputs/outputs (I/O8-I/O15 3.3 Address Latch Enable (AL 3.4 Command Latch Enable (CL 3.5 Chip Enable ( 3.6 Read Enable ( 3.7 Write Enable ( 3.8 Write Protect (WP 3.9 Ready/Busy (RB ...
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... Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.9 Read ONFI signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.10 Read parameter page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.1 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.2 NAND flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.3 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.4 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.5 Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.6 Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.6.1 8.6.2 9 Program and erase times and endurance cycles ...
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Contents 12 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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NAND01G-B2C List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3. TSOP48 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. VFBGA63 connections (top view through package Figure 5. VFBGA153 connections (top view through package Figure 6. Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 8. Read operations (intercepted Figure 9. Random data output during sequential data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 10. Cache read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 11 ...
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... Serial number (unique identifier), which allows the devices to be uniquely identified. Non-volatile protection to lock sensible data permanently. For more details of this option contact your nearest Numonyx sales office. These security features are subject to an NDA (non-disclosure agreement) and are, therefore, not described in the datasheet. For more details about them, refer to the nearest Numonyx sales office ...
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... NAND01G-B2C Timings Sequential Random Page Block access access Program erase time time time (typ) (max) (typ) (min) 25 µ µ 200 µ µ µ 1024-Mbit + 32Mbit NAND flash memory array Page buffer Y decoder Buffers I/O AI14291 Package VFBGA63 VFBGA153 TSOP48 (1) (1) ...
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NAND01G-B2C Figure 2. Logic diagram x16 organization only available for MCP. Table 3. Signal names Signal I/O8-15 Data input/outputs for x16 devices Data input/outputs, address inputs, or command inputs I/O0-7 for x8 and x16 devices AL ...
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Description Figure 3. TSOP48 connections 1. Only available for 3 V devices. 10/ NAND01G-B2C ...
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NAND01G-B2C Figure 4. VFBGA63 connections (top view through package Only available for 3 V devices ...
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Description Figure 5. VFBGA153 connections (top view through package ⎯ VSS C VSS A12 ...
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... NAND01G-B2C 2 Memory array organization The memory array is made up of two NAND structures where 32 cells are connected in series. The memory array is organized in blocks where each block contains 64 pages. The array is split into two areas, the main area and the spare area. The main area of the array is used to store data whereas the spare area is typically used to store error correction codes, software flags or bad block identification ...
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... Memory array organization Figure 6. Memory array organization x8 DEVICES Block = 64 pages Page = 2112 bytes (2048 + 64) Main area Block Page 2048 bytes Page buffer, 2112 bytes 2,048 bytes 14/67 Block Page 8 bits 64 bytes 64 8 bits bytes NAND01G-B2C x16 DEVICES Block = 64 pages Page = 1056 words (1024 + 32) ...
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... When CL is High, the inputs are latched on the rising edge of Write Enable. 3.5 Chip Enable (E) The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is Low, V High while the device is busy, the device remains selected and does not go into IH standby mode ...
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... 3.10 V supply voltage DD V provides the power supply to the internal core of the memory device the main DD power supply for all operations (read, program and erase). An internal voltage detector disables all functions whenever V Table 22 and Table power-transitions. Each device in a system should have V widths should be sufficient to carry the required program and erase currents ...
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... See Figure 23 and 4.4 Data output Data output bus operations are used to read: the data in the memory array, the status register, the electronic signature and the unique identifier. Table 5: Bus operations, for a summary. Table 24 for details of the timings requirements. Table 24 for details of the timings requirements ...
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... Write Protect bus operations are used to protect the memory against program or erase operations. When the Write Protect signal is Low the device will not accept program or erase operations and so the contents of the memory array cannot be altered. The Write Protect signal is not latched by Write Enable to ensure protection even during power-up. ...
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NAND01G-B2C Table 7. Address insertion, x16 devices I/O8- Bus (1) cycle I/O15 Any additional address input cycles will be ignored. Table 8. Address definitions, x8 devices Table ...
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Command set 5 Command set All bus write operations to the device are interpreted by the command interface. The commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal ...
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... Device operations The following section gives the details of the device operations. 6.1 Read memory array At power-up the device defaults to read mode. To enter read mode from another mode the Read command must be issued, see Once a Read command is issued two types of operations are available: random read and page read ...
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Device operations Figure 7. Read operations Add.N Add.N I/O 00h cycle 1 cycle 2 Command Address N input code 22/67 tBLBH1 Data Add.N Add.N 30h N cycle 3 cycle 4 Command Busy from address ...
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NAND01G-B2C Figure 8. Read operations (intercepted Col. I/O 00h Add 1 Column Address tWHBH tWHBL tBLBH1 Busy Col. Row Row 30h Add 2 Add 1 Add 2 Row Address Device operations tEHCLX ...
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Device operations Figure 9. Random data output during sequential data output Col Col Row I/O 00h Add 2 Add 1 Add 1 Command code 4 Add cycles Row Add 1,2 Col Add 1,2 24/67 ...
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NAND01G-B2C 6.2 Cache read The cache read operation is used to improve the read throughput by reading data using the cache register. Since the device has only one cache register, serial data output on one page may be executed while ...
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... R/B 6.3 Page program The page program operation is the standard operation to program data to the memory array. Within a given block, the pages must be programmed sequentially. Random page address programming is not recommended. The memory array is programmed by page, however partial page programming is allowed where any number of bytes (1 to 2112) or words (1 to 1056) can be programmed ...
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NAND01G-B2C 6.3.2 Random data input in a page During a sequential input operation, the next sequential address to be programmed can be replaced by a random address, by issuing a Random Data Input command. The following two steps are required ...
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Device operations Figure 12. Random data input during sequential data input RB Address I/O 80h Data Intput Inputs Cmd Code 4 Add cycles Row Add 1,2 Col Add 1,2 Main area 28/67 tBLBH2 (Program Busy time) Address 85h Data Input ...
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... The copy back program operation is used to copy the data stored in one page and reprogram it in another page. The copy back program operation does not require external memory and so the operation is faster and more efficient because the reading and loading cycles are not required. The operation is particularly useful when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned block ...
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Device operations Figure 14. Page copy back program with random data input Source I/O 35h 00h Add Inputs Read Code tBLBH1 (Read Busy time) RB 6.5 Block erase Erase operations are done one block at a time. An erase operation ...
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... The Reset command is used to reset the command interface and status register. If the Reset command is issued during any operation, the operation will be aborted was a program or erase operation that was aborted, the contents of the memory locations being modified will no longer be valid as the data will be partially programmed or erased. ...
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... The error bit is used to identify if any errors have been detected by the P/E/R controller. The error bit is set to ’1’ when a program or erase operation has failed to write the correct data to the memory. If the error bit is set to ‘0’ the operation has completed successfully. 6.7.5 SR4, SR3, SR2, and SR1 are reserved Table 11 ...
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NAND01G-B2C 6.8 Read electronic signature The device contains a manufacturer code and device code. To read these codes three steps are required: 1. One bus write cycle to issue the Read Electronic Signature command (90h) 2. One bus write cycle ...
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Device operations Table 14. Electronic signature byte/word 4 I/O I/O1-I/O0 I/O2 I/O3 I/O5-I/O4 I/O6 I/O7 6.9 Read ONFI signature To recognize NAND flash devices that are compatible with ONFI 1.0 command set, the Read Electronic Signature command can be issued, ...
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NAND01G-B2C Figure 16. Read ONFI signature waveforms I/O 90h Read Electronic Signature command 6.10 Read parameter page The Read Parameter Page command retrieves the data structure that describes the NAND flash organization, features, timings and ...
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Device operations Figure 17. Read parameter page waveforms I/O0-7 ECh 00h R/B 36/ ... tBLBH1 NAND01G-B2C ... ai14409 ...
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NAND01G-B2C Table 16. Parameter page data structure Byte 0-3 4-5 6-7 8-9 10-31 32-43 44-63 64 65-66 67-79 (1) O/M Parameter page signature – Byte 0: 4Fh, ‘O’ M – Byte 1: 4Eh, ‘N’ – Byte 2: 46h, ‘F’ – ...
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Device operations Table 16. Parameter page data structure (continued) Byte 80-83 84-85 86-89 90-91 92-95 96-99 100 101 102 103-104 105-106 107 108-109 110 111 112 113 114 115-127 38/67 (1) O Number ...
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NAND01G-B2C Table 16. Parameter page data structure (continued) Byte 128 129-130 131-132 133-134 135-136 137-138 139-140 141-163 164-165 166-253 254-255 256-511 512-767 768 optional mandatory. (1) O/M M Timing mode support Bit 6 to bit ...
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... It features a Write Protect, WP, pin, which can be used to protect the device against program and erase operations recommended to keep down. In addition, to protect the memory from any involuntary program/erase operations during power-transitions, the device has an internal voltage detector which disables all functions whenever V is below V ...
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... Table 18 algorithms to extend the number of program and erase cycles and increase data retention. To help integrate a NAND memory into an application, Numonyx can provide a full range of software solutions: file system, sector manager, drivers and code management. Contact the nearest Numonyx sales office or visit www.numonyx.com for more details. ...
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Software algorithms Table 17. NAND flash failure modes Operation Erase Program Read Figure 18. Bad block management flowchart Figure 19. Garbage collection Valid page Invalid page 42/67 Procedure Block replacement Block replacement or ECC START Block Address = Block 0 ...
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... After several updates it is necessary to remove invalid pages to free some memory space. To free this memory space and allow further program operations it is recommended to implement a garbage collection algorithm garbage collection software the valid pages are copied into a free area and the block containing the invalid pages is erased (see Figure 19) ...
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Software algorithms These models provide information such as AC characteristics, rise/fall times and package mechanical data, all of which are measured or simulated at voltage and temperature ranges wider than those allowed by target specifications. IBIS models are used to ...
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NAND01G-B2C 9 Program and erase times and endurance cycles The program and erase times and the number of program/erase cycles per block are shown in Table 18. Table 18. Program, erase times and program erase endurance cycles Parameters Page program ...
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Maximum ratings 10 Maximum ratings Stressing the device above the ratings listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the ...
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NAND01G-B2C 11 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under ...
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DC and AC parameters Figure 20. Equivalent testing circuit for AC characteristics measurement 48/67 NAND flash C L GND NAND01G-B2C ref 2R ref GND Ai11085 ...
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NAND01G-B2C Table 22. DC characteristics, 1.8 V devices Symbol Parameter I DD1 Operating current I DD2 I DD3 I Standby current (CMOS) DD5 I Input leakage current LI I Output leakage current LO V Input high voltage IH V Input ...
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DC and AC parameters Table 24. AC characteristics for command, address, data input Alt. Symbol symbol t Address Latch Low to Write Enable High ALLWH t ALS t Address Latch High to Write Enable High ALHWH Command Latch High to ...
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NAND01G-B2C Table 25. AC characteristics for operations Alt. Symbol symbol t Address Latch Low to ALLRL1 t AR Read Enable Low t ALLRL2 t t Ready/Busy High to Read Enable Low BHRL RR t Busy time during cache read BLBHx ...
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DC and AC parameters 1. The time to ready depends on the value of the pull-up resistor tied to the ready/busy pin. See Figure 36 the time from W rising edge during the final address cycle to ...
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NAND01G-B2C Figure 22. Address Latch AC waveforms CL tELWH (E Setup time) E tWLWH W tALHWH (AL Setup time) AL tDVWH (Data Setup time) I/O Figure 23. Data Input Latch AC waveforms CL E tALLWH (ALSetup time) AL tWLWH W ...
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DC and AC parameters Figure 24. Sequential data output after read AC waveforms E R tRLQV (R Accesstime) I/O tBHRL Low Low High. Figure 25. Serial access cycle after read, for frequency ...
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NAND01G-B2C Figure 26. Read status register AC waveforms CL tCLHWH E tELWH W R tDVWH (Data Setup time) I/O Figure 27. Read electronic signature AC waveforms I/O 90h Read Electronic Signature Command 1. Refer to ...
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DC and AC parameters Figure 28. Page read operation AC waveforms CL E tWLWL Add.N Add.N I/O 00h cycle 1 cycle 2 Command Address N input code 56/67 tWHBL tALLRL2 tWHBH tRLRH tBLBH1 Data Add.N Add.N ...
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NAND01G-B2C Figure 29. Page program AC waveforms CL E tWLWL (Write Cycle time Add.N I/O 80h cycle 1 RB Page Program setup code tWLWL tWHWH Add.N Add.N Add.N N cycle 4 cycle 2 cycle 3 Address Input ...
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DC and AC parameters Figure 30. Block erase AC waveforms CL E tWLWL (Write Cycle time I/O 60h RB Block Erase Setup command Figure 31. Reset AC waveforms I/O FFh RB 58/67 tBLBH3 ...
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NAND01G-B2C Figure 32. Program/erase enable waveforms W tVHWH WP RB I/O Figure 33. Program/erase disable waveforms W tVLWH WP High RB I/O 11.1 Ready/Busy signal electrical characteristics Figure 35, Figure 34 signal. The value required for the resistor R So, ...
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DC and AC parameters Figure 34. Ready/Busy AC waveform Figure 35. Ready/Busy load circuit Figure 36. Resistor value versus waveform timings for Ready/Busy signal 25°C. 60/67 ready busy ...
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... NAND01G-B2C 11.2 Data protection The Numonyx NAND device is designed to guarantee data protection during power transitions detection circuit disables all NAND operations the V range from V DD low ( guarantee hardware protection during power transitions as shown in the below IL figure. Figure 37. Data protection Nominal Range ...
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... Package mechanical 12 Package mechanical To meet environmental requirements, Numonyx offers these devices in RoHS compliant packages, which have a lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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NAND01G-B2C Figure 39. VFBGA63 1. +15, 0.80 mm pitch, package outline FD1 BALL "A1" 1. Drawing is not to scale Table 27. VFBGA63 1.05 ...
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Package mechanical Figure 40. VFBGA153 0 132+21 3R14, 0.50 mm pitch, package outline and mechanical data 64/67 NAND01G-B2C MIN NOM MAX A 0.90 A1 0.15 0.58 A2 0.25 0.30 0.35 Øb D 7.90 8.00 ...
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... F = RoHS compliant package, tape & reel packing 1. x16 organization only available for MCP products. Note: Not all combinations are necessarily available. For a list of available devices or for further information on any aspect of these products, please contact your nearest Numonyx sales office. Ordering information NAND01GW3B2C ZA ...
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Revision history 14 Revision history Table 29. Document revision history Date Version 24-Jun-2008 16-Jan-2009 23-Feb-2009 08-Jun-2009 29-Jan-2010 66/67 1 Initial release. Modified Section 8.5: Error correction 2 waveform, and Figure 36: Resistor value versus waveform timings for Ready/Busy signal. Removed ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...