M24C64-RMB6TG STMicroelectronics, M24C64-RMB6TG Datasheet - Page 21
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M24C64-RMB6TG
Manufacturer Part Number
M24C64-RMB6TG
Description
IC EEPROM 64KBIT 400KHZ 8MLP
Manufacturer
STMicroelectronics
Datasheet
1.M24C64-WMN6TP.pdf
(44 pages)
Specifications of M24C64-RMB6TG
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
64K (8K x 8)
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-MLP, 8-UFDFPN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
4.13
4.14
4.15
4.16
4.17
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure
condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges
this, and outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory
address 00h.
Read Identification Page (M24C64-D)
The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
The Identification Page can be read by issuing an Read Identification Page instruction. This
instruction uses the same protocol and format as the Random Address Read (from memory
array) with device type identifier defined as 1011b. The MSB address bits A15/A5 are don't
care, the LSB address bits A4/A0 define the byte address inside the Identification Page. The
number of bytes to read in the ID page must not exceed the page boundary (e.g.: when
reading the Identification Page from location 10d, the number of bytes should be less than
or equal to 22, as the ID page boundary is 32 bytes).
If the Identification Page is locked, the data bytes are read as FFh.
12) but without sending a Stop condition. Then, the bus master sends another Start
12, without acknowledging the Byte.
Figure
Doc ID 16891 Rev 23
12.
Device operation
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