CY7C1550V18-375BZC Cypress Semiconductor Corp, CY7C1550V18-375BZC Datasheet

Page 1

... K and K. Read data is driven on the rising edges of both K and K. Each address location is associated with two 8-bit words (CY7C1546V18), 9-bit words (CY7C1557V18), 18-bit words (CY7C1548V18), or 36-bit words (CY7C1550V18) that burst sequentially into or out of the device. Asynchronous inputs include output impedance matching input (ZQ) ...

Page 2

... Document Number: 001-06550 Rev. *D Write Write Reg Reg Output Logic Control Read Data Reg Reg. Reg. 8 Reg. Write Write Reg Reg Output Logic Control Read Data Reg Reg. Reg. 9 Reg. CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 8 R [7:0] 8 QVLD 9 R [8:0] 9 QVLD Page [+] Feedback ...

Page 3

... Logic Block Diagram (CY7C1548V18 (20:0) Address Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [1:0] Logic Block Diagram (CY7C1550V18 (19:0) Address Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [3:0] Document Number: 001-06550 Rev. *D Write Write Reg ...

Page 4

... Pin Configuration The Pin Configuration for CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 follows DQ4 DQ5 H DOFF V V REF DDQ DQ6 DQ7 R TDO TCK DQ4 DQ5 H DOFF V V REF DDQ DQ6 DQ7 R TDO TCK A Note 2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level. ...

Page 5

... Pin Configuration The Pin Configuration for CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 follows DQ9 DQ10 DQ11 F NC DQ12 DQ13 H DOFF V V REF DDQ DQ14 L NC DQ15 DQ16 DQ17 R TDO TCK NC/144M DQ27 DQ18 DQ28 D NC DQ29 DQ19 DQ20 F NC DQ30 DQ21 G NC ...

Page 6

... These address inputs are multiplexed for both read and write operations. Internally, the device is organized arrays each for CY7C1546V18 arrays each for CY7C1557V18 arrays each 18) for CY7C1548V18, and arrays each 36) for CY7C1550V18. R/W Input Synchronous Read or Write Input. When LD is LOW, this input designates the access type (read Synchronous when R/W is HIGH, write when R/W is LOW) for loaded address ...

Page 7

... DD V Ground Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document Number: 001-06550 Rev. *D Pin Description output impedance are set to 0.2 x RQ, where resistor [x:0] CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 and enables DDQ Page [+] Feedback ...

Page 8

... Functional Overview The CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 are synchronous pipelined Burst SRAMs equipped with a DDR interface. Accesses for both ports are initiated on the Positive Input Clock (K). All synchronous input and output timing refer to the rising edge of the input clocks (K and K). ...

Page 9

... Source CLK Source CLK Echo Clock1/Echo Clock1 Echo Clock2/Echo Clock2 Truth Table The truth table for CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 follows. Operation Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. Read Cycle: (2.0 cycle Latency) Load address ...

Page 10

... NWS , NWS , BWS , BWS , BWS , and BWS CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 remains unaltered. [7:4] remains unaltered. [17:9] remains unaltered. [7:4] remains unaltered. [17:9] remains unaltered. [3:0] remains unaltered. [8:0] remains unaltered. [3:0] remains unaltered. ...

Page 11

... Write Cycle Descriptions The write cycle description table for CY7C1550V18 follows. BWS BWS BWS BWS L– – L– – L– – L– – L– – L– – Document Number: 001-06550 Rev Comments – During the data portion of a write sequence, all four bytes (D the device. L– ...

Page 12

... Instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, the TAP controller is moved into the Update-IR state. CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 “TAP Controller Block Diagram” on page 15. Reset. ) when the SS on page 18 shows the order of the bits “ ...

Page 13

... PRELOAD. Document Number: 001-06550 Rev. *D CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 The shifting of data for the SAMPLE and PRELOAD phases occur concurrently when required — that is, while data captured is shifted out, the preloaded data is shifted in. BYPASS When the BYPASS instruction is loaded in the Instruction register and the TAP is placed in a Shift-DR state, the Bypass register is placed between the TDI and TDO pins ...

Page 14

... The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-06550 Rev. *D [10] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page [+] Feedback ...

Page 15

... TAP Controller Test Conditions = −2 −100 µ 2 100 µ GND ≤ V ≤ − /2). Undershoot: V (AC) > 0.3V (pulse width less than t CYC IL CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 Selection TDO Circuitry Min Max Unit 1.4 V 1.6 V 0.4 V 0.2 V 0.65V –0.3 0.35V V DD µA –5 5 “ ...

Page 16

... Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 001-06550 Rev. *D Description Figure 2. TAP Timing and Test Conditions 0.9V 50Ω 1. TMSH t TMSS t TDIS t TDIH t TDOV / ns CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 Min Max Unit MHz [15] ALL INPUT PULSES 0.9V t TCYC ...

Page 17

... Places the Bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-06550 Rev. *D Value CY7C1557V18 CY7C1548V18 000 000 00000110100 00000110100 1 1 Description CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 Description CY7C1550V18 000 Version number. SRAM. 00000110100 Enables unique identification of SRAM vendor. 1 Indicates the presence register. Bit Size 109 Page ...

Page 18

... CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 Bit Number Bump 100 2P 101 1P 102 3R 103 4R 104 4P 105 5P 106 5N 107 5R 108 Internal Page [+] Feedback ...

Page 19

... SRAM behavior. To avoid this, provide 2048 cycles stable clock to relock to the desired clock frequency. REF Figure 3. Power Up Waveforms > 2048 Stable Clock DDQ Stable (< + 0.1V DC per 50 ns) Fix HIGH (tie to V DDQ ) CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 . KC Var Start Normal Operation Page [+] Feedback ...

Page 20

... CYC (min) within 200 ms. During this time V < V and /2)/(RQ/5) for values of 175Ω < RQ < 350Ω. (max) = 0.95V or 0.54V , whichever is smaller. REF DDQ CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 Ambient [16 DDQ Temperature ( 0°C to +70°C 1.8 ± 0.1V 1. –40°C to +85°C ...

Page 21

... OUTPUT Device 0.25V 5 pF Under ZQ Test RQ = 250Ω INCLUDING JIG AND (b) SCOPE /I and load capacitance shown in ( Test Loads and OL OH, CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 Min Typ Max Unit V + 0.2 – 0.24 V REF DDQ –0.24 – V – 0.2 V REF Max Unit = 1.5V 5 ...

Page 22

... An input jitter of 200 ps (t KHKH Waveforms. Transition is measured ±100 mV from steady-state voltage. AC Test Loads and and t less than t . CLZ CHZ CO CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 375 MHz 333 MHz 300 MHz Unit Min Max Min Max Min Max 1 – 1 – 1 – ...

Page 23

... Document Number: 001-06550 Rev. *D NOP NOP NOP WRITE QVLD Q00 Q01 Q10 Q11 D20 D21 t t DOH CHZ CQD t CQDOH t CCQO t CCQO CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 WRITE READ NOP NOP QVLD D30 D31 Q40 Q41 t t CQH CQHCQH DON’T CARE UNDEFINED Page [+] Feedback ...

Page 24

... Not all of the speed, package, and temperature ranges are available. Contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code 375 CY7C1546V18-375BZC CY7C1557V18-375BZC CY7C1548V18-375BZC CY7C1550V18-375BZC CY7C1546V18-375BZXC CY7C1557V18-375BZXC CY7C1548V18-375BZXC CY7C1550V18-375BZXC CY7C1546V18-375BZI CY7C1557V18-375BZI CY7C1548V18-375BZI CY7C1550V18-375BZI CY7C1546V18-375BZXI CY7C1557V18-375BZXI CY7C1548V18-375BZXI ...

Page 25

... Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 Operating Range Commercial Industrial Page [+] Feedback ...

Page 26

... Package Diagram Document Number: 001-06550 Rev. *D Figure 6. 165-Ball FBGA ( 1.40 mm) CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 51-85195-*A Page [+] Feedback ...

Page 27

... Document History Page Document Title: CY7C1546V18/CY7C1557V18/CY7C1548V18/CY7C1550V18, 72-Mbit DDR-II+ SRAM 2-Word Burst Architec- ture (2.0 Cycle Read Latency) Document Number: 001-06550 Issue Orig. of REV. ECN No. Date Change ** 432718 See ECN NXR *A 437000 See ECN IGS *B 461934 See ECN NXR *C 497567 See ECN ...