HYI25D256160CE-5 Qimonda, HYI25D256160CE-5 Datasheet - Page 16

• Manufacturer Part Number: HYI25D256160CE-5
• Description: IC DDR SDRAM 256MBIT 66TSOP
• Manufacturer: Qimonda

Specifications of HYI25D256160CE-5

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1021-2

1) Used to mask write data; provided coincident with the corresponding data.
1)
2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (
Notes
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
4. All states and sequences not shown are illegal or reserved.
Rev. 2.4, 2007-07
03062006-8CCM-VPUW
Name (Function)
Write Enable
Write Inhibit
Current State
Self Refresh
Self Refresh
Power Down
Power Down
All Banks Idle
All Banks Idle
Bank(s) Active
V
clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
REF
must be maintained during Self Refresh operation
CKE n-1
Previous Cycle
L
L
L
L
H
H
H
H
CKEn
Current Cycle
L
H
L
H
L
L
L
H
Command n
X
Deselect or NOP
X
Deselect or NOP
Deselect or NOP
AUTO REFRESH
Deselect or NOP
See
16
Table 13
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L)
Action n
Maintain Self-Refresh
Exit Self-Refresh
Maintain Power-Down
Exit Power-Down
Precharge Power-Down Entry
Self Refresh Entry
Active Power-Down Entry
—
Truth Table 2: Clock Enable (CKE)
256 Mbit Double-Data-Rate SDRAM
Truth Table 1b: DM Operation
DM
L
H
t
XSNR
) period. A minimum of 200
Internet Data Sheet
DQs
Valid
X
TABLE 11
TABLE 12
Note
1)
1)
Note
1)
2)
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