DP8421AV-25 National Semiconductor, DP8421AV-25 Datasheet - Page 13

• Manufacturer Part Number: DP8421AV-25
• Description: IC CTRLR/DVR CMOS PROGRAM 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8421AV-25

• Controller Type: Dynamic RAM (DRAM)
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP8421AV-25

4 0 Port A Access Modes
The DP8420A 21A 22A have two general purpose access
modes Mode 0 RAS synchronous and Mode 1 RAS asyn-
chronous One of these modes is selected at programming
through the B1 input A Port A access to DRAM is initiated
by two input signals ADS (ALE) and CS The access is al-
ways terminated by one signal AREQ These input signals
should be synchronous to the input clock
4 1 ACCESS MODE 0
Mode 0 synchronous access is selected by negating the
input B1 during programming (B1
access ALE is pulse high and CS is asserted If precharge
time was met a refresh of DRAM or a Port B access was
not in progress the RAS (RASs) would be asserted on the
e
0) To initiate a Mode 0
FIGURE 8a Access Mode 0
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first rising edge of clock If a refresh or a Port B access is in
progress or precharge time is required the controller will
wait until these events have taken place and assert RAS
(RASs) on the next positive edge of clock
Sometime after the first positive edge of clock after ALE and
CS have been asserted the input AREQ must be asserted
In single port applications once AREQ is asserted CS can
be negated On the other hand ALE can stay asserted sev-
eral periods of clock however ALE must be negated before
or during the period of CLK in which AREQ is negated
The controller samples AREQ on the every rising edge of
clock after DTACK is asserted The access will end when
AREQ is sampled negated
TL F 8588 – 60