X3101V28 Intersil, X3101V28 Datasheet - Page 10

• Manufacturer Part Number: X3101V28
• Description: IC PROTECT/MONITOR 3CELL 28TSSOP
• Manufacturer: Intersil

Specifications of X3101V28

• Function: Battery Monitor
• Battery Type: Lithium-Ion (Li-Ion)
• Voltage - Supply: 6 V ~ 24 V
• Operating Temperature: -20°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Cell Number Selection
The X3100 is designed to operate with four (4) Li-Ion battery
cells. The X3101 is designed to operate with three (3) Li-ion
battery cells. The CELLN bit of the configuration register
(Table 9) sets the number of cells recognized. For the
X3101, the value for CELLN should always be zero.
Table 9. Selection of Number of Battery Cells
The configuration register consists of 16 bits of
NOVRAM memory (Table 2, Table 3). This memory
features a high-speed static RAM (SRAM) overlaid bit-
for-bit with non-volatile “Shadow” EEPROM. An auto-
matic array recall operation reloads the contents of the
shadow EEPROM into the SRAM configuration regis-
ter upon power-up (Figure 1).
Configuration
Register Bit
1. In the case that the X3100 or X3101 is configured for use with
CELLN
only three Li-Ion battery cells (i.e. CELLN = 0), then VCELL4
(pin 7) MUST be tied to Vss (pin 9) to ensure correct operation.
1
0
4 Li-Ion battery cells (X3100 default)
3 Li-Ion battery cells (X3100 or X3101)
10
Operation
1
X3100, X3101
Figure 1. Power-up of
The configuration register is designed for unlimited
write operations to SRAM, and a minimum of
1,000,000 store operations to the EEPROM. Data
retention is specified to be greater than 100 years.
It should be noted that the bits of the shadow
EEPROM are for the dedicated use of the configura-
tion register, and are NOT part of the general purpose
4kbit EEPROM array.
T
ister, see Table 30 and section “X3100/X3101 SPI Serial
Communication” on page 23.
After writing to this register using a WCFIG instruction,
data will be stored only in the SRAM of the configura-
tion register. In order to store data in shadow
EEPROM, a WREN instruction, followed by a
EEWRITE to any address of the 4kbit EEPROM mem-
ory array must occur, see Figure 2. This sequence ini-
tiates an internal nonvolatile write cycle which permits
data to be stored in the shadow EEPROM cells. It
must be noted that even though a EEWRITE is made
to the general purpose 4kbit EEPROM array, the value
and address to which it is written, is unimportant. If this
procedure is not followed, the configuration register
will power-up to the last previously stored values fol-
lowing a power-down sequence.
he WCFIG command writes to the configuration reg-
Configuration Register (SRAM)
Upper Byte
Recall
Configuration Register
Lower Byte
Shadow EEPROM
Recall
January 3, 2008
FN8110.1