CP2403-GM Silicon Laboratories Inc, CP2403-GM Datasheet - Page 50

• Manufacturer Part Number: CP2403-GM
• Description: IC LCD DRIVER 32QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2403-GM

• Package / Case: 32-QFN
• Display Type: LCD
• Configuration: 64 Segment
• Interface: I²C, SMBus
• Current - Supply: 620µA
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1864-5

CP2400/1/2/3
9.1.
Normal mode should be used whenever the host controller is communicating with the CP2400/1/2/3. In this mode,
the device is fully functional and the host interface is capable of operating at full speed. Typical normal mode power
consumption is listed in Table 3.1 on page 12.
9.2.
In RAM Preservation Mode, the internal oscillator is disabled and the SmaRTClock oscillator provides the system
clock. RAM Preservation Mode should be used when the CP2400/1/2/3 needs to be active for a prolonged period
of time in which communication with the host microcontroller is not required. Examples of this include preserving
the contents of RAM or using the fully featured Active port match capabilities. LCD and SmaRTClock functionality
remains fully functional in RAM Preservation Mode. Interrupt latency does increase in this mode.
From Normal Mode, the device can be placed in RAM Preservation Mode using the following procedure:
From RAM Preservation Mode, the device can be returned to Normal Mode using the following procedure:
See Table 3.4 for RAM Preservation Mode wake-up time. When using the SPI Interface, the CLK pin may be tied to
NSS in order to wake the device from RAM Preservation Mode on NSS falling. The CLKOVR bit (MSCN.2) must be
set to logic 0 and the SmaRTClock must be enabled and running in order to place the device in RAM Preservation
Mode.
50
Normal Mode
RAM Preservation Mode
1. Drive the CLK pin LOW.
2. Write 0x07 to the IOSCCN register to synchronize the oscillator control logic.
3. Write 0x03 to the IOSCCN register to switch oscillator control to the CLK pin.
4. Write 0x05 to the CLKSL register to select SmaRTClock oscillator as the system clock.
5. Drive the CLK pin HIGH.
1. Drive the CLK pin LOW. This will force the system clock to Internal Oscillator divided by 1.
2. Write 0x06 to the IOSCCN register to force the internal oscillator to remain enabled.
Rev. 1.0