CP2403-GM Silicon Laboratories Inc, CP2403-GM Datasheet - Page 97

• Manufacturer Part Number: CP2403-GM
• Description: IC LCD DRIVER 32QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2403-GM

• Package / Case: 32-QFN
• Display Type: LCD
• Configuration: 64 Segment
• Interface: I²C, SMBus
• Current - Supply: 620µA
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1864-5

CP2400/1/2/3
13.2.1. Timer 1 SmaRTClock Oscillator Capture Mode
The Capture Mode in Timer 1 allows the SmaRTClock oscillator period to be measured against the system clock d
by 12. Setting TF1CEN to 1 enables the SmaRTClock Oscillator Capture Mode for Timer 1.
When Capture Mode is enabled, a capture event will be generated every 8 SmaRTClock oscillator cycles. When
the capture event occurs, the contents of Timer 1 (TMR1H:TMR1L) are loaded into the Timer 1 reload registers
(TMR3RLH:TMR3RLL) and the T1F interrupt flag is set (triggering an interrupt if Timer 1 interrupts are enabled).
By recording the difference between two successive timer capture values, the SmaRTClock period can be
determined with respect to the system clock divided by 12. The system clock divided by 12 should be much faster
than the SmaRTClock to achieve an accurate reading.
For example, if T1XCLK = 0b, and TF1CEN = 1b, Timer 1 will increment every 12 system clock cycles and capture
every 8 SmaRTClock cycles. If the system clock is 24.5 MHz and the SmaRTClock is 32.768 kHz, the difference
between two successive captures should be approximately 498 counts. Knowing the system clock frequency, the
SmaRTClock frequency can be estimated as:
(SYSCLK x 8 / 12) / Counts = (24500000 Hz x 8 / 12) / 498 = 16333333 / 498 = 32797 Hz.
This mode allows software to determine the SmaRTClock oscillator frequency when the SmaRTClock oscillator is
being used in self-oscillate mode without a crystal.
TCLK
TR1
TMR1L
TMR1H
SYSCLK / 12
Capture
TF1CEN
TMR1RLL TMR1RLH
Interrupt
SmaRTClock / 8
Figure 13.3. Timer 1 Capture Mode Block Diagram
Rev. 1.0
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