ICL7126CPL Intersil, ICL7126CPL Datasheet - Page 6

• Manufacturer Part Number: ICL7126CPL
• Description: IC ADC 3.5 DIGIT LCD LP 40-DIP
• Manufacturer: Intersil

Specifications of ICL7126CPL

• Display Type: LCD
• Configuration: 7 Segment
• Digits Or Characters: A/D 3.5 Digits
• Current - Supply: 70µA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Supply: -
• Interface: -
• Other names: ICL7126CPLIS

Detailed Description
Analog Section
Figure 4 shows the Functional Diagram of the Analog
Section for the ICL7126. Each measurement cycle is divided
into three phases. They are (1) auto-zero (A-Z), (2) signal
integrate (INT) and (3) de-integrate (DE).
Auto-Zero Phase
During auto-zero three things happen. First, input high and
low are disconnected from the pins and internally shorted to
analog COMMON. Second, the reference capacitor is
charged to the reference voltage. Third, a feedback loop is
closed around the system to charge the auto-zero capacitor
C
integrator, and comparator. Since the comparator is included
in the loop, the A-Z accuracy is limited only by the noise of
the system. In any case, the offset referred to the input is
less than 10µV.
Signal Integrate Phase
During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and low
are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO
for a fixed time. This differential voltage can be within a wide
common mode range: up to 1V from either supply. If, on the
other hand, the input signal has no return with respect to the
converter power supply, IN LO can be tied to analog
COMMON to establish the correct common mode voltage. At
the end of this phase, the polarity of the integrated signal is
determined.
AZ
to compensate for offset voltages in the buffer amplifier,
COMMON
IN LO
IN HI
31
32
30
V+
1µA
INT
INT
C
A-Z
REF
34
+
6
REF HI
36
DE-
DE+
A-Z
A-Z AND DE(±)
C
REF
FIGURE 4. ANALOG SECTION OF ICL7126
A-Z
DE+
DE-
35
REF LO
33
N
ICL7126
C
V -
REF
26
-
+
INPUT
HIGH
-
+
De-integrate Phase
The final phase is de-integrate, or reference integrate. Input
low is internally connected to analog COMMON and input
high is connected across the previously charged reference
capacitor. Circuitry within the chip ensures that the capacitor
will be connected with the correct polarity to cause the
integrator to output to return to zero. The time required for
the output to return to zero is proportional to the input signal.
Specifically, the digital reading displayed is:
Differential Input
The input can accept differential voltages anywhere within
the common mode range of the input amplifier, or specifically
from 0.5V below the positive supply to 1V above the negative
supply. In this range, the system has a CMRR of 86dB
typical. However, care must be exercised to assure the
integrator output does not saturate. A worst case condition
would be a large positive common mode voltage with a near
full-scale negative differential input voltage. The negative
input signal drives the integrator positive when most of its
swing has been used up by the positive common mode
voltage. For these critical applications the integrator output
swing can be reduced to less than the recommended 2V full
scale swing with little loss of accuracy. The integrator output
can swing to within 0.5V of either supply without loss of
linearity.
-
Display Count = 1000
BUFFER
28
R
INT
2.8V
V+
1
6.2V
29



-------------- -
V
V
REF
IN
A-Z
INTEGRATOR
INPUT
LOW
C



AZ
.
A-Z
-
+
COMPARATOR
27
INT
C
+
INT
TO
DIGITAL
SECTION
FN3084.5