CS5467-ISZ Cirrus Logic Inc, CS5467-ISZ Datasheet - Page 14

• Manufacturer Part Number: CS5467-ISZ
• Description: IC ENERGY METERING 1PHASE 28SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5467-ISZ

• Package / Case: 28-SSOP
• Input Impedance: 30 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 0.8V
• Voltage - I/o Low: 0.2V
• Current - Supply: 3.5mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Meter Type: Single Phase
• Output Voltage Range: 2.4 V to 2.6 V
• Input Voltage Range: 2.4 V to 2.6 V
• Input Current: 100 nA
• Power Dissipation: 500 mW
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1555 - BOARD EVAL FOR CS5467 ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1197-5

4. SIGNAL PATH DESCRIPTION
The data flow for voltage and current measurement and
the other calculations are shown in Figures 3, 4, and 5.
4.1 Analog-to-Digital Converters
Voltage1 channel and voltage2/temperature channel
use second-order delta-sigma modulators and the two
current channels use fourth-order delta-sigma modula-
tors to convert the analog inputs to single-bit digital data
streams. The converters sample at a rate of DCLK/8.
This high sampling provides a wide dynamic range and
simplifies anti-alias filter design.
4.2 Decimation Filters
The single-bit modulator output data is widened to 24
bits and down-sampled to DCLK/1024 with low-pass
decimation filters. These decimation filters are third-or-
der Sinc. Their outputs are passed through third-order
14
FGA
FGA
1
2
2
Figure 3. Signal Flow for V1, I1, P1, Q1 Measurements
Figure 4. Signal Flow for V2, I2, P2, Q2 Measurements
Control Register
V1
V2
I1
I2
VHPF1 IHPF1
OFF
OFF
VHPF2 IHPF2
OFF
OFF
IIR “anti-sinc” filters, used to compensate for the ampli-
tude roll-off of the decimation filters.
4.3 Phase Compensation
Phase compensation changes the phase of current rel-
ative to voltage by changing the sampling time in the
decimation filters. The amount of phase shift is set by
bits PC[7:0] in the Configuration register ( Config ) for
channel 1 and bits PC[7:0] in the Control register ( Ctrl )
for channel 2.
Phase compensation, PC[7:0] is a signed two’s comple-
ment binary value in the range of -1.0 to almost +1.0
output word rate (OWR) samples. For a sample rate of
4000 Hz, the delay range is ±250 uS, a phase shift of
±4.5° at 50 Hz and ±5.4° at 60 Hz. The step size would
be 0.0352° at 50 Hz and 0.0422° at 60 Hz at this sample
rate.
V1
V2
I1
I2
GAIN
GAIN
GAIN
GAIN
V2
I2
P2
CS5467
DS714F1
V2Q
Q2