ADE7763ARSZ Analog Devices Inc, ADE7763ARSZ Datasheet
ADE7763ARSZ
Specifications of ADE7763ARSZ
Available stocks
Related parts for ADE7763ARSZ
ADE7763ARSZ Summary of contents
Page 1
FEATURES High accuracy; supports IEC 61036/60687, IEC62053-21, and IEC62053-22 On-chip digital integrator enables direct interface-to-current sensors with di/dt output A PGA in the current channel allows direct interface to shunts and current transformers Active and apparent energy, sampled waveform, and ...
Page 2
ADE7763 TABLE OF CONTENTS Specifications ..................................................................................... 3 Timing Characteristics ..................................................................... 4 Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6 Terminology ...................................................................................... 7 Pin Configuration and Function Descriptions ............................. 8 Typical Performance Characteristics ........................................... 10 Theory of Operation ...................................................................... 13 ...
Page 3
SPECIFICATIONS ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL Table 1. Specifications Parameter ENERGY MEASUREMENT ACCURACY Active Power Measurement Error Channel 1 ...
Page 4
ADE7763 Parameter Signal-to-Noise Plus Distortion Bandwidth (–3 dB) REFERENCE INPUT REF Input Voltage Range IN/OUT Input Capacitance ON-CHIP REFERENCE Reference Error Current Source Output Impedance Temperature Coefficient CLKIN Input Clock Frequency LOGIC INPUTS RESET, DIN, SCLK, CLKIN, and CS Input ...
Page 5
TIMING CHARACTERISTICS ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL Table 2. Timing Characteristics Parameter Spec Write Timing ...
Page 6
ADE7763 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter AVDD to AGND DVDD to DGND DVDD to AVDD Analog Input Voltage to AGND V1P, V1N, V2P, and V2N Reference Input Voltage to AGND Digital Input ...
Page 7
TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7763 is defined by the following formula: Percent Error = ⎛ − Energy Register ADE7763 True ⎜ ⎜ True Energy ⎝ Phase Error between Channels The digital ...
Page 8
ADE7763 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 RESET Reset Pin reset condition. 2 DVDD Digital Power Supply. This pin provides the supply voltage for the digital circuitry. The supply voltage should ...
Page 9
Pin No. Mnemonic Description 14 IRQ Interrupt Request Output. This is an active low, open-drain logic output. Maskable interrupts include active energy register rollover, active energy register at half level, and arrivals of new waveform samples—see the Interrupts section. 15 ...
Page 10
ADE7763 TYPICAL PERFORMANCE CHARACTERISTICS 0.4 GAIN = 1 0.3 INTEGRATOR OFF INTERNAL REFERENCE 0.2 +25° 0.1 0 –0.1 –0.2 +25° 0.5 –0.3 +85° 0.5 –0.4 –0.5 –0.6 0 FULL-SCALE CURRENT (%) ...
Page 11
GAIN = 8 1.0 INTEGRATOR OFF INTERNAL REFERENCE 0.8 0 0.5 0.4 0 –0.2 –0.4 –0 FREQUENCY (Hz) Figure 12. Active Energy Error as a ...
Page 12
ADE7763 0.5 GAIN = 8 INTEGRATOR ON 0.4 INTERNAL REFERENCE 0.3 5.25V 0.2 0.1 5.00V 0 –0.1 –0.2 4.75V –0.3 –0.4 –0.5 0 FULL-SCALE CURRENT (%) Figure 18. Active Energy Error as a Percentage of Reading (Gain = ...
Page 13
THEORY OF OPERATION ANALOG INPUTS The ADE7763 has two fully differential voltage input channels. The maximum differential input voltage for input pairs V1P/V1N and V2P/V2N is ±0 addition, the maximum signal level on analog inputs for V1P/V1N and ...
Page 14
ADE7763 DC COMPONENT (INCLUDING ERROR TERM) IS EXTRACTED BY THE LPF FOR REAL POWER CALCULATION × × × × ω 0 2ω FREQUENCY (RAD/S) Figure 25. Effect ...
Page 15
FREQUENCY (Hz) Figure 29. Combined Phase Response of the Digital Integrator and Phase Compensator –1.0 –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 –4.5 –5.0 –5.5 –6 FREQUENCY (Hz) ...
Page 16
ADE7763 Zero-Crossing Timeout Zero-crossing detection has an associated timeout register, ZXTOUT. This unsigned, 12-bit register is decremented (1 LSB) every 128/CLKIN seconds. The register is reset to its user- programmed, full-scale value when a zero crossing on Channel 2 is ...
Page 17
LINE VOLTAGE SAG DETECTION In addition to detecting the loss of the line voltage when there are no zero crossings on the voltage channel, the ADE7763 can also be programmed to detect when the absolute value of the line voltage ...
Page 18
ADE7763 times the maximum absolute value observed on the Channel 2 input. The contents of IPEAK represent the maximum absolute value observed on the Channel 1 input. Reading the RSTVPEAK and RSTIPEAK registers clears their respective contents after the read ...
Page 19
Interrupt Timing Review the Serial Interface section before reading this section. As previously described, when the IRQ output goes low, the MCU ISR will read the interrupt status register to determine the source of the interrupt. When reading the status ...
Page 20
ADE7763 Antialias Filter Figure 39 also shows an analog low-pass filter (RC) on the input to the modulator. This filter prevents aliasing, which is an artifact of all sampled systems. Aliasing means that frequency components in the input signal to ...
Page 21
V1P PGA1 V1 V1N V1 0.5V, 0.25V, 0.125V, 62.5mV, 0x28 51EC 31.3mV, 15.6mV, 0V 0xD 7AE4 ANALOG INPUT RANGE *WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED DEPENDING ON THE SIGNAL FREQUENCY ...
Page 22
ADE7763 CURRENT SIGNAL (i(t)) 0x28 51EC 0x00 0xD7 AE14 CHANNEL 1 With the specified full-scale analog input signal of 0.5 V, the ADC produces an output code that is approximately ±2,642,412d— see the Channel 1 ADC section. The equivalent rms ...
Page 23
V2 ANALOG INPUT RANGE 0.5V, 0.25V, 0.125V, 62.5mV, 31.25mV CHANNEL 2 Channel 2 has only one analog input range (0.5 V differential). Like Channel 1, Channel 2 has a PGA with gain selections and 16. ...
Page 24
ADE7763 PHASE COMPENSATION When the HPF is disabled, the phase error between Channel 1 and Channel from dc to 3.5 kHz. When HPF is enabled, Channel 1 has the phase response illustrated in Figure 50 and Figure ...
Page 25
FREQUENCY (Hz) Figure 52. Combined Gain Response of HPF and Phase Compensation ACTIVE POWER CALCULATION Power is defined as the rate of energy flow from the ...
Page 26
ADE7763 CURRENT CHANNEL VOLTAGE CHANNEL T Figure 55 shows the signal processing chain for the active power calculation. The active power is calculated by low-pass filtering the instantaneous power signal. Note that when reading the waveform samples from the output ...
Page 27
I CURRENT SIGNAL – i(t) V VOLTAGE SIGNAL– v(t) The ADE7763 achieves the integration of the active power signal by continuously accumulating the active power signal in an internal unreadable 49-bit energy register. The active energy register (AENERGY[23:0]) represents the ...
Page 28
ADE7763 Integration Time under Steady Load As mentioned in the last section, the discrete time sample period ( T ) for the accumulation register is 1.1 μs (4/CLKIN). With full-scale sinusoidal signals on the analog inputs and the WGAIN register ...
Page 29
The active power signal (output of LPF2) can be rewritten as ⎡ ⎤ ⎢ ⎥ ⎢ ⎥ − × ⎢ ⎥ cos( ⎢ ⎥ 2 ⎛ ⎞ ⎢ + ⎥ ⎜ ...
Page 30
ADE7763 LINE CYCLE ENERGY ACCUMULATION MODE In line cycle energy accumulation mode, the energy accumu- lation of the ADE7763 can be synchronized to the Channel 2 zero crossing so that active energy accumulates over an integral number of half line ...
Page 31
APPARENT POWER CALCULATION The apparent power is the maximum power that can be delivered to a load. V and I are the effective voltage and rms rms current delivered to the load; the apparent power (AP) is defined as V ...
Page 32
ADE7763 APPARENT ENERGY CALCULATION The apparent energy is given as the integral of the apparent power. ∫ = Apparent Energy Apparent Power The ADE7763 achieves the integration of the apparent power signal by continuously accumulating the apparent power signal in ...
Page 33
Integration Times under Steady Load As mentioned in the last section, the discrete time sample period ( T ) for the accumulation register is 1.1 μs (4/CLKIN). With full-scale sinusoidal signals on the analog inputs and the VAGAIN register set ...
Page 34
ADE7763 ENERGIES SCALING The ADE7763 provides measurements of active and apparent energies. These measurements do not have the same scaling and therefore cannot be compared directly to each other. Table 7. Energies Scaling 0.707 Integrator ...
Page 35
Watt Gain The first step of calibrating the gain is to define the line voltage, the base current, and the maximum current for the meter. A meter constant, such as 3200 imp/kWh or 3.2 imp/Wh, needs to be determined for ...
Page 36
ADE7763 With the CFNUM register set to 0, CFDEN is calculated to be 489 for the example meter: ⎛ ⎞ CF ⎜ ⎟ − nominal ) CFDEN = INT 1 ⎜ ⎟ CF ⎝ ⎠ expected ...
Page 37
CALCULATE CFDEN VALUE FOR DESIGN WRITE CFDEN VALUE TO CFDEN REGISTER ADDR. 0x15 = CFDEN SET TEST b TEST NOM SET HALF LINE CYCLES FOR ACCUMULATION IN LINECYC REGISTER ...
Page 38
ADE7763 WGAI N is calculate 480 using Equation ⎛ ⎛ ⎞ 19186 − × ⎜ 12 ⎜ ⎟ WGAIN = INT 1 2 ⎝ ⎠ ⎝ 17174 Note that WGAIN is a signed, twos complement register With ...
Page 39
Calibrating Watt Offset with an Accurate Source Example Figure 74 is the flowchart for watt offset calibration with an accurate source. SET TEST MIN TEST NOM SET HALF LINE CYCLES FOR ACCUMULATION IN ...
Page 40
ADE7763 Phase Calibration The PHCAL register is provided to remove small phase errors. The ADE7763 compensates for phase error by inserting a small time delay or advance on the voltage channel input. Phase leads up to 1.84° and phase lags ...
Page 41
Calibrating Phase with an Accurate Source Example With an accurate source, line cycle accumulation is a good method of calibrating phase error. The value of LAENERGY must be obtained at two power factors and PF = 0.5 ...
Page 42
ADE7763 SET INTERRUPT ENABLE FOR ZERO CROSSING ADDR. 0x0A = 0x0010 RESET THE INTERRUPT STATUS READ REGISTER ADDR. 0x0C INTERRUPT? NO YES READ VRMS OR IRMS ADDR. 0x17; 0x16 RESET THE INTERRUPT STATUS READ REGISTER ADDR. 0x0C Figure 77. Synchronizing ...
Page 43
CALCULATE CFDEN VALUE FOR DESIGN WRITE CFDEN VALUE TO CFDEN REGISTER SET I SET HALF LINE CYCLES FOR ACCUMULATION IN LINECYC REGISTER ADDR. 0x1C ACCUMULATION ADDR. 0x09 = 0x0080 ENABLE LINE CYCLE ACCUMULATION INTERRUPT ADDR. 0x0A = 0x04 RESET THE ...
Page 44
ADE7763 SUSPENDING FUNCTIONALITY The analog and the digital circuit can be suspended separately. The analog portion can be suspended by setting the ASUSPEND bit (Bit 4) of the mode register to logic high—see the Mode Register (0x09) section. In suspend ...
Page 45
The serial interface of the ADE7763 is made up of four signals: SCLK, DIN, DOUT, and CS . The serial clock for a data transfer is applied at the SCLK logic input. This logic input has a Schmitt- trigger input ...
Page 46
ADE7763 Serial Read Operation During a data read operation from the ADE7763, data is shifted out at the DOUT logic output upon the rising edge of SCLK the case with the data write operation, a write to the ...
Page 47
REGISTERS Table 9. Summary of Registers by Address Address Name R/W No. Bits 0x01 WAVEFORM R 24 0x02 AENERGY R 24 0x03 RAENERGY R 24 0x04 LAENERGY R 24 0x05 VAENERGY R 24 0x06 RVAENERGY R 24 0x07 LVAENERGY R ...
Page 48
ADE7763 Address Name R/W No. Bits 0x11 APOS R/W 16 0x12 WGAIN R/W 12 0x13 WDIV R/W 8 0x14 CFNUM R/W 12 0x15 CFDEN R/W 12 0x16 IRMS R 24 0x17 VRMS R 24 0x18 IRMSOS R/W 12 0x19 VRMSOS ...
Page 49
Address Name R/W No. Bits 0x26 TEMP R 8 0x27 PERIOD R 16 0x28– 0x3C 0x3D TMODE R/W 8 0x3E CHKSUM R 6 0x3F DIEREV Type decoder unsigned signed by twos complement method, ...
Page 50
ADE7763 REGISTER DESCRIPTIONS All ADE7763 functionality is accessed via on-chip registers. Each register is accessed by first writing to the communication register and then transferring the register data. A full description of the serial interface protocol is given in the ...
Page 51
Bit Bit Default Location Mnemonic Value 14, 13 WAVSEL1 POAM 0 POAM (POSITIVE ONLY ACCUMULATION) WAVSEL (WAVEFORM SELECTION FOR SAMPLE MODE LPF2 01 = RESERVED 10 = CH1 11 = CH2 DTRT (WAVEFORM SAMPLES OUTPUT ...
Page 52
ADE7763 INTERRUPT STATUS REGISTER (0x0B), RESET INTERRUPT STATUS REGISTER (0x0C), INTERRUPT ENABLE REGISTER (0x0A) The status register is used by the MCU to determine the source of an interrupt request ( IRQ ). When an interrupt event occurs, the corresponding ...
Page 53
CH1OS REGISTER (0x0D) The CH1OS register is an 8-bit, read/write enabled register. The MSB of this register is used to switch the digital integrator on and off in Channel 1, and Bits indicate the amount of offset ...
Page 54
... ADE7763 OUTLINE DIMENSIONS 2.00 MAX 0.05 MIN COPLANARITY 0.10 ORDERING GUIDE Model Temperature Range 1 ADE7763ARSZ −40°C to +85°C ADE7763ARSZRL 1 −40°C to +85°C 1 EVAL-ADE7763EBZ RoHS Compliant Part. 7.50 7.20 6. 5.60 5.30 8.20 5.00 7.80 7. 1.85 1.75 1.65 8° 0.38 SEATING 4° ...
Page 55
NOTES Rev Page ADE7763 ...
Page 56
ADE7763 NOTES ©2004–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04481-0-8/09(B) Rev Page ...