ADE7758 Analog Devices, ADE7758 Datasheet
ADE7758
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ADE7758 Summary of contents
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... The ADE7758 is suitable to measure active, reactive, and apparent energy in various 3-phase configurations, such as WYE or DELTA services, both with three or four wires. The ADE7758 provides system calibration features for each phase, i ...
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... Reactive Power Calculation ...................................................... 35 Apparent Power Calculation..................................................... 38 Energy Registers Scaling ........................................................... 41 Waveform Sampling Mode ....................................................... 41 Calibration................................................................................... 41 Checksum Register..................................................................... 54 ADE7758 Interrupts................................................................... 54 Using the ADE7758 Interrupts with an MCU........................ 54 Interrupt Timing ........................................................................ 55 ADE7758 Serial Interface.......................................................... 55 ADE7758 Serial Write Operation ............................................ 56 ADE7758 Serial Read Operation ............................................. 57 Accessing the ADE7758 On-Chip Registers........................... 58 Communications Register......................................................... 58 Operational Mode Register (0x13) ...
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... Added Figure 73; Renumbered Subsequent Figures ..................38 Change to Gain Calibration Using Pulse Output Example .......44 Changes to Equation 37 .................................................................45 Changes to Example—Phase Calibration of Phase A Using Pulse Output..................................................................45 Changes to Equations 56 and 57 ...................................................53 Addition to the ADE7758 Interrupts Section .............................54 Changes to Example-Calibration of RMS Offsets ......................54 Addition to Table 20 .......................................................................66 Rev Page ADE7758 ...
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... This mode permits faster and more accurate calibration by synchronizing the energy accumulation with an integer number of line cycles. Data is read from the ADE7758 via the SPI serial interface. The interrupt request output ( IRQ ) is an open-drain, active low logic output. The IRQ output goes active low when one or more interrupt events have occurred in the ADE7758 ...
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... All specifications CLKIN of 10 MHz 15 MHz max 5 MHz min 2.4 V min DVDD = 5 V ± 5% 0.8 V max DVDD = 5 V ± 5% ±3 µA max Typical 10 nA max Rev Page ADE7758 −40°C to +85°C. MIN MAX pin IN/OUT = DVDD IN ...
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... ADE7758 Parameter LOGIC OUTPUTS IRQ, DOUT, and CLKOUT Output High Voltage Output Low Voltage APCF and VARCF Output High Voltage Output Low Voltage POWER SUPPLY AVDD DVDD See the Terminology section for a definition of the parameters. ...
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... Minimum time between data byte transfers during a multibyte read. Data access time after SCLK rising edge following a write to the communications register. Bus relinquish time after falling edge of SCLK. Bus relinquish time after rising edge of CS. and the ADE7758 Serial Interface section. 200µ ...
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... ADE7758 SCLK DIN COMMAND BYTE SCLK DIN DOUT COMMAND BYTE DB7 A1 MOST SIGNIFICANT BYTE Figure 3. Serial Write Timing DB7 MOST SIGNIFICANT BYTE Figure 4. Serial Read Timing Rev ...
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... maximum rating conditions for extended periods may affect device reliability. –0 AVDD + 0.3 V –0 DVDD + 0.3 V –0 DVDD + 0.3 V –40°C to +85°C –65°C to +150°C 150° 53°C/W 215°C 220°C Rev Page ADE7758 ...
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... This quiet ground reference should be used for all analog circuitry, for example, antialiasing filters, current, and voltage transducers. In order to keep ground noise around the ADE7758 to a minimum, the quiet ground plane should only be connected to the digital ground plane at one point acceptable to place the entire device on the analog ground plane ...
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... Chip Select. Part of the 4-wire serial interface. This active low logic input allows the ADE7758 to share the serial bus with several other devices (see the ADE7758 Serial Interface section). 22 DIN Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK (see the ADE7758 Serial Interface section). 23 SCLK Serial Clock Input for the Synchronous Serial Interface ...
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... Gain Error The gain error in the ADCs of the ADE7758 is defined as the difference between the measured ADC output code (minus the offset) and the ideal output code (see the Current Channel ADC and Voltage Channel ADC sections) ...
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... LINE FREQUENCY (Hz) Frequency with Internal Reference and Integrator Off 0. 0.08 0.06 0. 5.25V 0.02 DD –0 –0.2 –0.04 –0. 4.75V DD –0.08 –0.10 0.01 0.1 1 PERCENT FULL-SCALE CURRENT (%) Power Supply with Internal Reference and Integrator Off ADE7758 10 100 100 ...
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... ADE7758 0. 0.20 0.15 PHASE A 0.10 0.05 0 –0.05 PHASE B –0.10 –0.15 –0.20 –0.25 0.01 0.1 1 PERCENT FULL-SCALE CURRENT (%) Figure 12. APCF Error as a Percentage of Reading (Gain = +1) with Internal Reference and Integrator Off 0.4 0.3 0.2 0 +25 ° –40 ° C –0.1 –0 +85 ° C –0.3 –0.4 0.01 0.1 1 PERCENT FULL-SCALE CURRENT (%) Figure 13 ...
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... Figure 23. Active Energy Error as a Percentage of Reading (Gain = +4) over Power Factor with Internal Reference and Integrator On Rev Page ADE7758 –40°C +25°C +85°C 0 PERCENT FULL-SCALE CURRENT (%) PF = +0.5, –40° +0.5, +25° –0.5, +25° +1, +25° +0.5, +85° ...
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... ADE7758 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0.01 0.1 1 PERCENT FULL-SCALE CURRENT (%) Figure 24. Reactive Energy Error as a Percentage of Reading (Gain = +4) over Temperature with Internal Reference and Integrator On 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0 LINE FREQUENCY (Hz) Figure 25. Active Energy Error as a Percentage of Reading (Gain = +4) over Frequency with Internal Reference and Integrator On 1 ...
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... SD: 3.2985 Rev Page MEAN: 6.5149 SD: 2.816 – PhB OFFSET (mV) Figure 32. Phase B Channel 1 Offset Distribution MEAN: 6.69333 SD: 2.70443 PhC OFFSET (mV) Figure 33. Phase C Channel 1 Offset Distribution ADE7758 12 14 ...
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... B 10 Ω 5 Ω 2.5 Ω 1.25 Ω Figure 34. Test Circuit for Integrator Off µ F 100nF APCF AVDD DVDD VARCF 1k Ω 1k Ω IAP 5 33nF 33nF ADE7758 1k Ω 1k Ω IAN 6 33nF 33nF CLKOUT IBP 7 SAME CLKIN AP AN IBN 8 ICP DOUT 9 SAME AS I ...
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... This is usually sufficient to eliminate the effects of aliasing. ANALOG INPUTS The ADE7758 has a total of six analog inputs divided into two channels: current and voltage. The current channel consists of three pairs of fully differential voltage inputs: IAP and IAN, IBP and IBN, and ICP and ICN. These fully differential voltage input pairs have a maximum differential signal of ± ...
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... WSMP bit in the interrupt mask register to Logic 1, the interrupt request output IRQ goes active low when a sample is available. The timing is shown in Figure 40. The 24-bit waveform samples are transferred from the ADE7758 one byte (8-bits time, with the most significant byte shifted out first. IRQ ...
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... The current signal needs to be recovered from the di/dt signal before it can be used. An integrator is therefore necessary to restore the signal to its original form. The ADE7758 has a built- in digital integrator to recover the current signal from the di/dt sensor. The digital integrator on Channel 1 is switched on by default when the ADE7758 is powered up ...
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... A more effective antialiasing filter is needed to avoid noise due to aliasing (see the Theory of Operation section). When the digital integrator is switched off, the ADE7758 can be used directly with a conventional current sensor, such as a current transformer (CT low resistance current shunt. ...
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... IRQ goes active low when a sample is available. Figure 40 shows the timing. The 24-bit waveform samples are transferred from the ADE7758 one byte (8 bits time, with the most significant byte shifted out first. The sign of the register is extended in the upper 8 bits. The timing is the same as that for the current channels (see Figure 40) ...
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... The ADE7758 provides a means of digitally calibrating these small phase errors. The ADE7758 allows a small time delay or time advance to be introduced into the signal processing chain in order to compensate for the small phase errors. ...
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... Figure 54. Phase Response of the HPF and Phase Compensation ( Hz) 0.10 0.08 0.06 0.04 0.02 0 –0. FREQUENCY (Hz) Figure 55. Gain Response of HPF and Phase Compensation ( Hz) ACTIVE AND REACTIVE ENERGY CALCULATION µ VA DELAYED BY 4 ° (–0.104 @ 60Hz) IA 0x7C 60Hz ADE7758 ...
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... SAG detection level at 0. The detection of a decrease of an input voltage is in this case disabled. PEAK VOLTAGE DETECTION The ADE7758 can record the peak of the voltage waveform and produce an interrupt if the current exceeds a preset limit. Peak Voltage Detection Using the VPEAK Register The peak absolute value of the voltage waveform within a fixed number of half-line cycles is stored in the VPEAK register ...
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... POWER-SUPPLY MONITOR The ADE7758 also contains an on-chip power-supply monitor. The analog supply (AVDD) is monitored continuously by the ADE7758. If the supply is less than 4 V ± 5%, the ADE7758 goes into an inactive state, that is, no energy is accumulated when the supply voltage is below 4 V. This is useful to ensure correct device operation at power-up and during power-down ...
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... For time sampling signals, rms calculation involves squaring the signal, taking the average, and obtaining the square root. FRMS The method used to calculate the rms value in the ADE7758 is to low-pass filter the square of the input signal (LPF3) and take the square root of the result (see Figure 62). ...
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... Additionally, this measurement has a bandwidth of 14 kHz. Current RMS Offset Compensation The ADE7758 incorporates a current rms offset compensation for each phase (AIRMSOS, BIRMSOS, and CIRMSOS). These are 12-bit signed registers that can be used to remove offsets in the current rms calculations ...
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... P is referred to as the active or real power. Note that the active power is equal to the dc component of the instantaneous power signal p(t) in Equation 5, that is, VRMS × IRMS. This is the relationship used to calculate the active power in the ADE7758 for each phase. The instantaneous power signal p(t) is generated by multiplying the current and voltage signals in each phase. ...
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... Phase A is negative, Bit 14 for Phase B, and Bit 13 for Phase C. No-Load Threshold The ADE7758 has an internal no-load threshold on each phase. The no-load threshold can be activated by setting the NOLOAD bit (Bit 7) of the COMPMODE register. If the active power falls below 0.005% of full-scale input, the energy is not accumulated in that phase ...
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... By setting the AEHF bit (Bit 0) of the interrupt mask register, T (9) ⎭ the ADE7758 can be configured to issue an interrupt ( IRQ ) when Bit 14 of any one of the three watt-hr accumulation registers has changed, indicating that the accumulation register is half full (positive or negative). Setting the RSTREAD bit (Bit 6) of the LCYMODE register enables a read-with-reset for the watt-hr accumulation registers, i ...
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... Wye 0 Different gain calibration parameters are offered in the ADE7758 to cover the calibration of the meter in different configurations. It should be noted that in CONSEL Mode 0d the IGAIN and WGAIN registers have the same effect on the end result. However, changing IGAIN also changes all other calculations that use the current waveform ...
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... When using the line cycle accumulation mode, the RSTREAD bit (Bit 6) of the LCYCMODE register should be set to Logic 0. WG[11:0] WDIV[7: WATTHR[15:0] CALIBRATION CONTROL LINECYC[15:0] Figure 70. ADE7758 Line Cycle Active Energy Accumulation Mode Rev Page ⎡ ⎢ × ⎢ VRMS IRMS = × × – ...
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... Calibration section). The number of zero crossings is specified by the LINECYC register. LINECYC is an unsigned 16-bit register. The ADE7758 can accumulate active power for up to 65535 combined zero crossings. Note that the internal zero crossing counter is always active ...
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... VAR calculation. The ADE7758 has a sign detection circuit for the reactive power calculation. The REVPRP bit (Bit 18) in the interrupt status register is set if the average reactive power from any one of the phases changes ...
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... By setting the REHF bit (Bit 1) of the mask register, the ADE7758 can be configured to issue an interrupt ( IRQ ) when Bit 14 of any one of the three VAR-hr accumulation registers has changed, indicating that the accumulation register is half full (positive or negative) ...
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... Figure 68 illustrates the energy-to-frequen ADE7758. Note that the input to the DFC can be selected between the total reactive power and total apparent power. Therefore, the VARCF pin can output frequency that is ...
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... VA-hr accumulation registers contents can roll over to 0 and continue increasing in value. By setting the VAEHF bit (Bit 2) of ⎞ ⎟ the mask register, the ADE7758 can be configured to issue an ⎠ interrupt ( IRQ ) when the MSB of any one of the three VA-hr accumulation registers has changed, indicating that the accumulation register is half full ...
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... IGAIN should not be used when using CONSEL Mode 0, COMPMODE[0:1]. Apparent Power Frequency Output Pin 17 (VARCF) of the ADE7758 can provide frequency output for the total apparent power. By setting the VACF bit (Bit 7) of the WAVMODE register, this pin provides an output frequency that is directly proportional to the total apparent power ...
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... ADE7758 (APCF or VARCF) and the pulse output of the reference meter or CF EXPECTED Figure 76 shows a flow chart of how to calibrate the ADE7758 using the pulse output. Since the pulse outputs are proportional to the total energy in all three phases, each phase must be cali- brated individually ...
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... ADE7758 YES ALL PH YES NO WATT OFFSET CAL? SET UP PULSE OUTPUT FOR A, B, AND C END CALIBRATE WATT OFFSET @ I MIN Gain Calibration Using Pulse Output Gain calibration is used for meter-to-meter gain adjustment, APCF or VARCF output rate calibration, and determining the Wh/LSB, VARh/LSB, and VAh/LSB constant. The registers used for watt gain calibration are CFNUM (0x45), CFDEN (0x46), and xWG (0x2A to 0x2C) ...
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... ALL NO STEP 3 SET UP PULSE OUTPUT FOR PHASE YES CFNUM/VARCFNUM SET TO CALCULATE VALUES? STEP 5 SET UP SYSTEM FOR TEST STEP 6 MEASURE % ERROR FOR APCF AND VARCF STEP 7 CALCULATE AND WRITE TO XWG, XVAG CALCULATE Wh/LSB AND VAh/LSB CONSTANTS ADE7758 NOM ...
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... V and I are the values of current and voltage, which FULLSCALE correspond to the full scale ADC inputs of the ADE7758. θ is the angle between the current and the voltage channel, and the APCF value is equivalent to the reference meter output EXPECTED under the test conditions ...
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... Phase Step 5: Calculate xPHCAL xPHCAL not known, the period is available in the ADE7758’s frequency register, FREQ (0x10). Equation 37 shows how to determine the value that needs to be written to xPHCAL using the period register measurement. In Equation 37, the 2.4 µs is for phase errors that are negative. For positive phase errors, the 2.4 µ ...
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... ADE7758 YES END Step 1: Repeat Step 1 and Step 3 from the gain calibration to configure the ADE7758 pulse output. Step 2: Set the xWATTOS and xVAROS registers to Logic 0. Step 3: Set the test system for TEST MIN factor. For Step 6, set the test system for I zero-power factor ...
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... LINECYC interrupt. The benefit of using this mode is that the sinusoidal component of the active energy is eliminated. Figure 80 shows a flow chart of how to calibrate the ADE7758 using the line accumulation mode. Calibration of all phases and energies can be done simultaneously using this mode to save time during calibration ...
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... READ FREQUENCY REGISTER Step 1: Set xWG, xVARG, and xVAG to Logic 0. Step 2: Set up ADE7758 for line accumulation by writing 0x3F to LCYCMODE. This enables the line accumulation mode on the xWATTHR, xVAHR, and xVARHR (0x01 to 0x03) registers by setting the LWATT, LVAR, and LVA bits, LCYCMODE[0:2] (0x17), to Logic 1 ...
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... Phase Calibration Using Line Accumulation (45) The ADE7758 includes a phase calibration register on each phase to compensate for small phase errors. Large phase errors should be compensated by adjusting the antialiasing filters. The ADE7758’s phase calibration is a time delay with different weights in the positive and negative direction (see the Phase Compensation section) ...
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... Step 6: Calculate xPHCAL and write to the xPHCAL registers (0x3F to 0x41). The period is available in the ADE7758 frequency register not known. Equation 37 shows how to determine the value written to xPHCAL using the period register measurement (see the Phase Calibration Using Pulse Output section). In Equation 37, the 2.4 µ ...
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... MIN I – I MIN TEST × Offset xWATTOS × AccumTime CLKIN is the value in the energy register at I TEST is the value in the energy register at I MIN , V , and zero power factor TEST NOM ADE7758 × MIN TEST (52) × (53) , and TEST . MIN ...
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... The low-pass filter used to obtain the rms measurements is not ideal, therefore it is recommended to synchronize the readings with the zero crossings of the voltage waveform and to average a few measurements when reading the rms registers. The ADE7758 IRMS measurement is linear over a 500:1 range, and the VRMS measurement is linear over a 20:1 range 220 V, NOM ...
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... TEST MAX/X × – − = × NOM NOM/20 RMS 64 V – V NOM/20 and V are the rms register values NOM-RMS NOM/20-RMS NOM ADE7758 ) × − TEST RMS 2 (56) , respectively. × V − NOM/20 NOM RMS NOM (57) and V , NOM/20-RMS ...
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... This is achieved by carrying out a read from RSTATUS, Address 0x1A. The IRQ output goes logic high on completion of the interrupt status register read command (see the Interrupt Timing section). When carrying out a read with reset, the ADE7758 is designed to ensure that no = − . ...
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... All data transfer operations are synchronized to the serial clock. Data is shifted into the ADE7758 at the DIN logic input on the falling edge of SCLK. Data is shifted out of the ADE7758 at the DOUT logic output on a rising edge of SCLK. The CS logic input is the chip select input. This input is used when multiple devices share the serial bus ...
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... The seven LSBs of this byte contain the address of the register to be written to. The ADE7758 starts shifting in the register data on the next falling edge of SCLK. All remaining bits of register data are shifted in on the falling edge of the subsequent SCLK pulses (see Figure 91) ...
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... ADE7758 SERIAL READ OPERATION During a data read operation from the ADE7758, data is shifted out at the DOUT logic output on the rising edge of SCLK. As was the case with the data write operation, a data read must be preceded with a write to the communications register. With the ADE7758 in communications mode and CS logic low, an 8-bit write to the communications register first takes place ...
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... W/R When this bit is a Logic 1, the data transfer operation immediately following the write to the communications register is interpreted as a write to the ADE7758. When this bit is a Logic 0, the data transfer operation immediately following the write to the communications register is interpreted as a read operation. ...
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... VA-Hr (see Table 18). 0 The IRQ Mask Register. It determines if an interrupt event generates an active- low output at the IRQ pin (see the ADE7758 Interrupts section). 0 The IRQ Status Register. This register contains information regarding the source of the ADE7758 interrupts (see the ADE7758 Interrupts section). ...
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... ADE7758 Address 1 [A6:A0] Name R/W Length 0x23 GAIN R/W 8 0x24 AVRMSGAIN R/W 12 0x25 BVRMSGAIN R/W 12 0x26 CVRMSGAIN R/W 12 0x27 AIGAIN R/W 12 0x28 BIGAIN R/W 12 0x29 CIGAIN R/W 12 0x2A AWG R/W 12 0x2B BWG R/W 12 0x2C CWG R/W 12 0x2D AVARG R/W 12 0x2E BVARG R/W 12 0x2F CVARG R/W 12 0x30 AVAG R/W 12 0x31 BVAG R/W 12 0x32 CVAG R/W 12 0x33 AVRMSOS R/W 12 0x34 BVRMSOS R/W 12 0x35 ...
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... R/W: Read/write capability of the register. R: Read-only register. R/W: Register that can be both read and written. OPERATIONAL MODE REGISTER (0x13) The general configuration of the ADE7758 is defined by writing to the OPMODE register. Table 14 summarizes the functionality of each bit in the OPMODE register. Table 14. OPMODE Register Bit ...
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... PKVLVL or PKILVL registers, the corresponding bit(s) in the STATUS registers are set (see the Peak Current Detection section). WAVEFORM MODE REGISTER (0x15) The waveform sampling mode of the ADE7758 is defined by writing to the WAVMODE register. Table 16 summarizes the functionality of each bit in the WAVMODE register. Table 16. WAVMODE Register ...
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... COMPUTATIONAL MODE REGISTER (0x16) The computational method of the ADE7758 is defined by writing to the COMPMODE register. Table 17 summarizes the functionality of each bit in the COMPMODE register. Table 17. COMPMODE Register Bit Bit Default Location Mnemonic Value Description CONSEL 0 These bits are used to select the input to the energy accumulation registers. ...
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... ADE7758 LINE CYCLE ACCUMULATION MODE REGISTER (0x17) The functionalities involved the line-cycle accumulation mode in the ADE7758 are defined by writing to the LCYCMODE register. Table 18 summarizes the functionality of each bit in the LCYCMODE register. Table 18. LCYCMODE Register Bit Bit Default Location Mnemonic Value 0 LWATT ...
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... INTERRUPT MASK REGISTER (0x18) When an interrupt event occurs in the ADE7758, the IRQ logic output goes active low if the mask bit for this event is Logic 1 in the MASK register. The IRQ logic output is reset to its default collector open state when the RSTATUS register is read. Table 19 describes the function of each bit in the interrupt mask register ...
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... INTERRUPT STATUS REGISTER (0x19)/RESET INTERRUPT STATUS REGISTER (0x1A) The interrupt status register is used to determine the source of an interrupt event. When an interrupt event occurs in the ADE7758, the corresponding flag in the interrupt status register is set logic high. The IRQ pin goes active low if the corresponding bit in the interrupt mask register is set logic high ...
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... COPLANARITY 0.10 ORDERING GUIDE Model Temperature Range ADE7758ARW −40° 85°C ADE7758ARWRL −40° 85°C 1 ADE7758ARWZ −40° 85°C 1 ADE7758ARWZRL −40° 85°C EVAL-ADE7758EB Pb-free part. 15.60 (0.6142) 15.20 (0.5984 7.60 (0.2992) 7.40 (0.2913) 10.65 (0.4193 10.00 (0.3937) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) ...
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... ADE7758 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04443–0–9/04(A) Rev Page ...