ADE7758 Analog Devices, ADE7758 Datasheet - Page 20

• Manufacturer Part Number: ADE7758
• Description: Poly Phase Multifunction Energy Metering IC with Per Phase Information
• Manufacturer: Analog Devices

ADE7758
CURRENT CHANNEL ADC
Figure 41 shows the ADC and signal processing path for the
input IA of the current channels (same for IB and IC). In
waveform sampling mode, the ADC outputs are signed twos
complement 24-bit data-words at a maximum of 26.0 kSPS
(thousand samples per second). With the specified full-scale
analog input signal of ±0.5 V, the ADC produces its maximum
output code value (see Figure 41). This diagram shows a full-
scale voltage signal being applied to the differential inputs IAP
and IAN. The ADC output swings between 0xD7AE14
(−2,642,412) and 0x2851EC (+2,642,412).
Current Waveform Gain Registers
There is a multiplier in the signal path in the current channel
for each phase. The current waveform can be changed by ±50%
by writing a twos complement number to the 12-bit signed
current waveform gain registers (AIGAIN[11:0], BIGAIN[11:0],
and CIGAIN[11:0]). For example, if 0x7FF is written to those
registers, the ADC output is scaled up by +50%. On the other
hand, writing 0x800 scaled by the output –50%. The expression
below describes mathematically the function of the current
waveform gain registers.
Changing the content of AIGAIN[11:0], BIGAIN[11:0], or
CIGAIN[11:0] affects all calculations based on its current, i.e., it
affects the phase’s active/reactive/apparent energy as well as its
current rms calculation. In addition, waveform samples are also
scaled accordingly.
Current
ADC
Output
0.5V/GAIN
0.25V/GAIN
0.125V/GAIN
Waveform
×
V
IN
⎛
⎜
⎝
0V
1
V
IAP
IAN
+
IN
=
ANALOG
INPUT
RANGE
Content
PGA1
GAIN[1:0]
×
1,
×
of
2,
×
Current
4
GAIN[4:3]
2.42V, 1.21V, 0.6V
REFERENCE
2
12
ADC
Gain
0xD7AE14
0x2851EC
AIGAIN[11:0]
0x000000
Register
Figure 41. Current Channel Signal Path
CHANNEL 1
(CURRENT WAVEFORM)
DATA RANGE
ADC OUTPUT
WORD RANGE
Rev. A | Page 20 of 68
⎞
⎟
⎠
HPF
INTEGRATOR*
DIGITAL
GAIN[7]
Current Channel Sampling
The waveform samples of the current channel can be routed to
the WFORM register at fixed sampling rates by setting the
WAVSEL[2:0] bit in the WAVMODE register to 000 (binary).
The phase in which the samples are routed is set by setting the
PHSEL[1:0] bits in the WAVMODE register. Energy calculation
remains uninterrupted during waveform sampling.
When in waveform sample mode, one of four output sample
rates may be chosen by using Bit 5 and Bit 6 of the WAVMODE
register (DTRT[1:0]). The output sample rate may be 26.0 kSPS,
13.0 kSPS, 6.5 kSPS, or 3.3 kSPS (see Table 16). By setting the
WSMP bit in the interrupt mask register to Logic 1, the interrupt
request output IRQ goes active low when a sample is available.
The timing is shown in Figure 40. The 24-bit waveform samples
are transferred from the ADE7758 one byte (8-bits) at a time,
with the most significant byte shifted out first.
The interrupt request output IRQ stays low until the interrupt
routine reads the reset status register (see ADE7758 Interrupts).
DOUT
SCLK
IRQ
DIN
0xCB2E48
0xD4176D
0x34D1B8
0x2BE893
Figure 40. Current Channel Waveform Sampling
0x000000
0x000000
60Hz
50Hz
CURRENT RMS (IRMS)
CALCULATION
WAVEFORM SAMPLE
REGISTER
ACTIVE AND REACTIVE
POWER CALCULATION
READ FROM WAVEFORM
0
CHANNEL 1 (CURRENT WAVEFORM)
DATA RANGE AFTER INTEGRATOR
(60Hz AND AIGAIN[11:0] = 0x000)
12Hex
CHANNEL 1 (CURRENT WAVEFORM)
DATA RANGE AFTER INTEGRATOR
(50Hz AND AIGAIN[11:0] = 0x000)
CURRENT CHANNEL DATA–24 BITS
SGN