ADE7758 Analog Devices, ADE7758 Datasheet - Page 33

• Manufacturer Part Number: ADE7758
• Description: Poly Phase Multifunction Energy Metering IC with Per Phase Information
• Manufacturer: Analog Devices

Integration Time Under Steady Load
The discrete time sample period (T) for the accumulation
register is 0.4 µs (4/CLKIN). With full-scale sinusoidal signals
on the analog inputs and the watt gain registers set to 0x000, the
average word value from each LPF2 is 0xCCCCD (see Figure 64
and Figure 66). The maximum value which can be stored in the
watt-hr accumulation register before it overflows is 2
0x7FFF. Because the average word value is added to the internal
register, which can store 2
overflows, the integration time under these conditions with
WDIV = 0 is calculated as
When WDIV is set to a value different from 0, the time before
overflow is scaled accordingly as shown in Equation 10.
Energy Accumulation Mode
The active power accumulated in each watt-hr accumulation
register (AWATTHR, BWATTHR, or CWATTHR) depends on
the configuration of the CONSEL bits in the COMPMODE
register (Bit 0 and Bit 1). The different configurations are
described in Table 6.
Table 6. Inputs to Watt-Hr Accumulation Registers
CONSEL[1, 0]
00
01
10
11
Note that the contents of the watt-hr accumulation registers are
affected by both the current gain register (IGAIN) and the watt
gain register of the corresponding phase. IGAIN should not be
used when using Mode 0 of CONSEL, COMPMODE[0:1].
Depending on the poly phase meter service, the appropriate
formula should be chosen to calculate the active energy. The
American ANSI C12.10 standard defines the different
configurations of the meter.
Table 7 describes which mode should be chosen in these
different configurations.
Table 7. Meter Form Configuration
ANSI Meter Form
5S/13S
6S/14S
8S/15S
9S/16S
Time
Time
=
=
0xFF,
Time
3-Wire Delta
4-Wire Wye
4-Wire Delta
4-Wire Wye
0xCCCCD
AWATTHR
VA × IA
VA × (IA – IB)
VA × (IA – IB)
Reserved
FFFF,
(
WDIV
FFFF
40
=
− 1 or 0xFF, FFFF, FFFF before it
0
)
×
×
0.4
WDIV
BWATTHR
VB × IB
0
0
Reserved
CONSEL (d)
0
1
2
0
μs
=
[
0.524
7
0 :
]
second
CWATTHR
VC × IC
VC × (IC – IB)
VC × IC
Reserved
TERMSEL (d)
3, 5, or 6
7
7
7
15
− 1 or
(10)
Rev. A | Page 33 of 68
Different gain calibration parameters are offered in the
ADE7758 to cover the calibration of the meter in different
configurations. It should be noted that in CONSEL Mode 0d
the IGAIN and WGAIN registers have the same effect on the
end result. However, changing IGAIN also changes all other
calculations that use the current waveform. In other words,
changing IGAIN changes the active, reactive, and apparent
energy, as well as the RMS current calculation results.
Active Power Frequency Output
Pin 1 (APCF) of the ADE7758 provides frequency output
for the total active power. After initial calibration during
manufacturing, the manufacturer or end customer will often
verifies the energy meter calibration. One convenient way to
verify the meter calibration is for the manufacturer to provide
an output frequency that is proportional to the energy or active
power under steady load conditions. This output frequency can
provide a simple, single-wire, optically isolated interface to
external calibration equipment. Figure 68 illustrates the energy-
to-frequency conversion in the ADE7758.
A digital-to-frequency converter (DFC) is used to generate the
APCF pulse output from the total active power. TERMSEL bits
(Bit 2 to Bit 4) of the COMPMODE register can be used to select
which phases to include in the total power calculation. Setting
Bit 2, Bit 3, and Bit 4 includes the input to the AWATTHR,
BWATTHR, and CWATTHR registers in the total active power
calculation. The total active power is signed addition. However,
setting the ABS bit (Bit 5) in the COMPMODE register enables
the absolute only mode, that is, only the absolute value of the
active power is considered.
The output from the DFC is divided down by a pair of frequency
division registers before sending to the APCF pulse output.
Namely, APCFDEN/APCFNUM pulses are needed at the DFC
output before the APCF pin outputs a pulse. Under steady load
conditions, the output frequency is directly proportional to the
total active power. The pulse width of APCF is 64 × CLKIN if
APCFNUM and APCFDEN are both equal. If APCFDEN is
greater than APCFNUM, the pulse width depends on
APCFDEN. The pulse width in this case is T × (APCFDEN/2),
where T is the period of the APCF pulse and APCFDEN/2 is
rounded to the nearest whole number. An exception to this is
when the period is greater than 180 ms. In this case, the pulse
width is fixed at 90 ms.
INPUT TO BWATTHR
INPUT TO CWATTHR
INPUT TO AWATTHR
Figure 68. ADE7758 Active Power Frequency Output
REGISTER
REGISTER
REGISTER
+
+
+
DFC
APCFNUM[11:0]
APCFDEN[11:0]
÷
÷
4
ADE7758
APCF