ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 66

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7854/ADE7858/ADE7868/ADE7878
I
The write operation using the I
ADE7858/ADE7868/ADE7878 initiate when the master generates
a start condition and consists in one byte representing the
address of the ADE78xx followed by the 16-bit address of the
target register and by the value of the register.
The most significant seven bits of the address byte constitute
the address of the ADE7854/ADE7858/ADE7868/ADE7878
and they are equal to 0111000b. Bit 0 of the address byte is a
2
C Write Operation
S
0
SLAVE ADDRESS
1 1 1 0 0 0 0
A
C
K
15
REGISTER ADDRESS
MS 8 BITS OF
2
C interface of the ADE7854/
8
A
C
K
7
REGISTER ADDRESS
LS 8 BITS OF
Figure 81. I
0
2
C Write Operation of a 32-Bit Register
A
C
K
Rev. D | Page 66 of 96
31
OF REGISTER
BYTE 3 (MS)
ACKNOWLEDGE
GENERATED BY
ADE78xx
16
read/ write bit. Because this is a write operation, it has to be
cleared to 0; therefore, the first byte of the write operation is
0x70. After every byte is received, the ADE7854/ADE7858/
ADE7868/ADE7878 generate an acknowledge. As registers can
have 8, 16, or 32 bits, after the last bit of the register is transmitted
and the ADE78xx acknowledges the transfer, the master gene-
rates a stop condition. The addresses and the register content
are sent with the most significant bit first. See
details of the I
A
C
K
15
BYTE 2 OF REGISTER
2
C write operation.
8
A
C
K
BYTE 1 OF REGISTER
7
0
A
C
K
7
BYTE 0 (LS) OF
REGISTER
Figure 81
0
A
C
K
S
for