LT4254IGN Linear Technology, LT4254IGN Datasheet
LT4254IGN
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LT4254IGN Summary of contents
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... The PWRGD output indicates when the output voltage rises above a programmed level. An external resistor string from V overvoltage protection. , LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Q1 ...
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... V GATE CC CC 20V ≤ V ≤ 36V CC FB High-to-Low Transition FB Low-to-High Transition I = 1.6mA 5mA TOP VIEW ORDER PART NUMBER LT4254CGN 15 SENSE LT4254IGN GATE PART MARKING TIMER 4254 4254I GN PACKAGE = 125°C, θ = 130°C/W JA http://www.linear.com/leadfree/ MIN TYP MAX ● 10.8 1.9 ● ...
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ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at T SYMBOL PARAMETER I PWRGD Pin Leakage Current PWRGD I FB Input Current INFB I TIMER Pull-Up Current TIMERPU I TIMER Pull-Down Current TIMERPD V TIMER Shut-Down Threshold Voltage THTIMER D Duty ...
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LT4254 W U TYPICAL PERFOR A CE CHARACTERISTICS I vs Temperature CC 2 36V 24V CC 1 10.8V CC 1.6 1.4 1.2 1.0 –50 – 125 100 TEMPERATURE (°C) ...
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W U TYPICAL PERFOR A CE CHARACTERISTICS TIMER Pin Pull-Up Current vs Temperature –80 –90 –100 –110 –120 –130 –140 –150 –50 – 100 125 TEMPERATURE (°C) 4254 G13 TIMER Shutdown Threshold vs Temperature 5.0 4.8 ...
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LT4254 W U TYPICAL PERFOR A CE CHARACTERISTICS OV Threshold Voltage (High-to- Low) vs Temperature 3.70 3.65 3.60 3.55 3.50 –50 – 100 125 TEMPERATURE (°C) 4254 G22 OPEN Pin Threshold Voltage vs Temperature 5.0 4.5 ...
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CTIO S reaches 4.65V (typ), the GATE pin is pulled low; the TIMER pull-up current will be turned off and the capacitor is dis- charged by a 3µA pull-down current. When the TIMER pin falls ...
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LT4254 W BLOCK DIAGRA GEN REF GEN 4V 7 RETRY – INTERNAL + 9.8V + 0.65V – + – 4.65V 8 SENSE 15 + ...
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TEST CIRCUIT DIAGRA PLHUV V +2V OUT GATE Figure GATE Timing APPLICATIO S I FOR ATIO Hot Circuit Insertion When circuit boards are inserted ...
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LT4254 U U APPLICATIO S I FOR ATIO V IN 24V (SHORT PIN) C3 0.1µF GND Resistor R7 compensates the current control loop while R6 prevents high frequency oscillations in Q1. When the power pins first make contact, transistor Q1 ...
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U U APPLICATIO S I FOR ATIO V – SENSE 50mV 12mV 0V 2V Figure 7. Current Limit Sense Voltage vs Feedback Pin Voltage Layout Considerations section for important information about board layout to minimize current limit threshold ...
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LT4254 U U APPLICATIO S I FOR ATIO Latch Off Operation I OUT 500mA/DIV TIMER 5V/DIV V OUT 20V/DIV GATE 20V/DIV 2.5ms/DIV Figure 9. Latch Off Waveforms commanded to start back up. This can be commanded by cycling the UV ...
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U U APPLICATIO S I FOR ATIO V CC (SHORT PIN) C3 0.1µF GND V LOGIC LT4254 R OPEN 4 INTERNAL OPEN COLLECTOR PULL-DOWN Figure 12. Delay Circuit for OPEN FET Detection LT4254 stays in current limit long enough for ...
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LT4254 U U APPLICATIO S I FOR ATIO V CC (SHORT PIN) C3 0.1µF GND Figure 14. Negative Output Voltage Protection Diode Application standard threshold MOSFET can be used. In applications from 12V to 15V range, a logic level MOSFET ...
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... FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. ...
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... Onboard 8-Bit ADC with Monitoring Onboard 10-Bit ADC with I www.linear.com ● V OUT C L 100µF R8 140k R9 R4 40.2k 27k 4254 F16 2 C Interface for Board Monitoring 2 C Interface for Board Monitoring 4254fb LT 1205 REV B • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2003 ...