PCA9533D/01,112 NXP Semiconductors, PCA9533D/01,112 Datasheet

IC LED DRIVER RGB 8-SOIC

PCA9533D/01,112

Manufacturer Part Number
PCA9533D/01,112
Description
IC LED DRIVER RGB 8-SOIC
Manufacturer
NXP Semiconductors
Type
RGB LED Driverr
Datasheet

Specifications of PCA9533D/01,112

Package / Case
8-SOIC (3.9mm Width)
Topology
Open Drain, PWM
Number Of Outputs
4
Internal Driver
Yes
Type - Primary
Backlight, LED Blinker
Type - Secondary
RGB
Frequency
400kHz
Voltage - Supply
2.3 V ~ 5.5 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 85°C
Current - Output / Channel
25mA
Internal Switch(s)
Yes
Low Level Output Current
25 mA
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Supply Current
550 uA
Maximum Power Dissipation
400 mW
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4003 - DEMO BOARD LED DIMMER568-3512 - DEMO BOARD UART TO I2C
Voltage - Output
-
Efficiency
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-3372-5
935274434112
PCA9533D/01
1. General description
2. Features
The PCA9533 is a 4-bit I
256 discrete steps for Red/Green/Blue (RGB) color mixing and back light applications.
The PCA9533 contains an internal oscillator with two user programmable blink rates and
duty cycles coupled to the output PWM. The LED brightness is controlled by setting the
blink rate high enough (> 100 Hz) that the blinking cannot be seen and then using the duty
cycle to vary the amount of time the LED is on and thus the average current through the
LED.
The initial setup sequence programs the two blink rates/duty cycles for each individual
PWM. From then on, only one command from the bus master is required to turn individual
LEDs ON, OFF, BLINK RATE 1 or BLINK RATE 2. Based on the programmed frequency
and duty cycle, BLINK RATE 1 and BLINK RATE 2 will cause the LEDs to appear at a
different brightness or blink at periods up to 1.69 second. The open-drain outputs directly
drive the LEDs with maximum output sink current of 25 mA per bit and 100 mA per
package.
To blink LEDs at periods greater than 1.69 second the bus master (MCU, MPU, DSP,
chip set, etc.) must send repeated commands to turn the LED on and off as is currently
done when using normal I/O expanders like the NXP Semiconductors PCF8574 or
PCA9554. Any bits not used for controlling the LEDs can be used for General Purpose
parallel Input/Output (GPIO) expansion, which provides a simple solution when additional
I/O is needed for ACPI power switches, sensors, push-buttons, alarm monitoring, fans,
etc.
The Power-On Reset (POR) initializes the registers to their default state, causing the bits
to be set HIGH (LED off).
Due to pin limitations, the PCA9533 is not featured with hardware address pins. The
PCA9533/01 and the PCA9533/02 have different fixed I
operation of both on the same bus.
I
I
I
I
I
I
PCA9533
4-bit I
Rev. 03 — 27 April 2009
4 LED drivers (on, off, flashing at a programmable rate)
Two selectable, fully programmable blink rates (frequency and duty cycle) between
0.591 Hz and 152 Hz (1.69 second and 6.58 milliseconds)
256 brightness steps
Input/outputs not used as LED drivers can be used as regular GPIOs
Internal oscillator requires no external components
I
2
C-bus interface logic compatible with SMBus
2
C-bus LED dimmer
2
C-bus and SMBus I/O expander optimized for dimming LEDs in
2
C-bus addresses allowing
Product data sheet

Related parts for PCA9533D/01,112

PCA9533D/01,112 Summary of contents

Page 1

... To blink LEDs at periods greater than 1.69 second the bus master (MCU, MPU, DSP, chip set, etc.) must send repeated commands to turn the LED on and off as is currently done when using normal I/O expanders like the NXP Semiconductors PCF8574 or PCA9554. Any bits not used for controlling the LEDs can be used for General Purpose ...

Page 2

... NXP Semiconductors I Internal power-on reset I Noise filter on SCL/SDA inputs I 4 open-drain outputs directly drive LEDs Edge rate control on outputs I No glitch on power-up I Supports hot insertion I Low standby current I Operating power supply voltage range 400 kHz clock frequency I ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per ...

Page 3

... NXP Semiconductors 4. Block diagram PCA9533 SCL INPUT FILTERS SDA POWER- RESET OSCILLATOR V SS Remark: Only one I/O shown for clarity. Fig 1. Block diagram of PCA9533 5. Pinning information 5.1 Pinning Fig 2. 5.2 Pin description Table 3. Symbol LED0 LED1 LED2 V SS LED3 PCA9533_3 Product data sheet ...

Page 4

... NXP Semiconductors Table 3. Symbol SCL SDA Functional description Refer to 6.1 Device address Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA9533/01 is shown in PCA9533/02 is shown in Fig 4. The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation ...

Page 5

... NXP Semiconductors 6.2.1 Control register definition Table 6.3 Register descriptions 6.3.1 INPUT - Input register The INPUT register reflects the state of the device pins. Writes to this register will be acknowledged but will have no effect. Table 5. Bit Symbol Default Remark: The default value ‘X’ is determined by the externally applied logic level (normally logic 1) when used for directly driving LED with pull- ...

Page 6

... NXP Semiconductors 6.3.4 PCS1 - Frequency Prescaler 1 PSC1 is used to program the period of the PWM output. The period of BLINK1 = (PSC1 + 1) / 152. Table 8. Bit Symbol Default 6.3.5 PWM1 - Pulse Width Modulation 1 The PWM1 register determines the duty cycle of BLINK1. The outputs are LOW (LED on) when the count is less than the value in PWM1 and HIGH (LED off) when it is greater ...

Page 7

... NXP Semiconductors 6.4 Pins used as GPIOs LEDn pins not used to control LEDs can be used as General Purpose I/Os (GPIOs). For use as input, set LEDn to high-impedance (00) and then read the pin state via the INPUT register. For use as output, connect external pull-up resistor to the pin and size it according to the DC recommended operating characteristics ...

Page 8

... NXP Semiconductors 7. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...

Page 9

... NXP Semiconductors SDA SCL MASTER TRANSMITTER/ RECEIVER Fig 9. System configuration 7.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse ...

Page 10

... NXP Semiconductors 7.4 Bus transactions SCL slave address (PCA9533/01) SDA START condition write to register data out from port Fig 11. Write to register slave address (PCA9533/01) SDA START condition acknowledge slave address (PCA9533/01) (cont (repeated) START condition Fig 12. Read from register slave address (PCA9533/01) ...

Page 11

... NXP Semiconductors 8. Application design-in information Fig 14. Typical application 8.1 Minimizing I When the I/Os are used to control LEDs, they are normally connected to V resistor as shown in I about 1.2 V less than V I lower than V Designs needing to minimize current consumption, such as battery power applications, ...

Page 12

... NXP Semiconductors 8.2 Programming example The following example will show how to set LED0 and LED1 off. It will set LED2 to blink duty cycle. LED3 will be set to be dimmed their maximum brightness (duty cycle = 25 %). PCA9533/01 is used in this example. Table 11. Program sequence START PCA9533 address ...

Page 13

... NXP Semiconductors 10. Static characteristics Table 13. Static characteristics Symbol Parameter Supplies V supply voltage DD I supply current DD I standby current stb I additional quiescent supply DD current V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current ...

Page 14

... NXP Semiconductors 20 % (1) percent variation (1) maximum (2) average (3) minimum Fig 17. Typical frequency variation over process 2 3 PCA9533_3 Product data sheet 002aac191 20 % percent variation 100 amb (1) maximum (2) average (3) minimum Fig 18. Typical frequency variation over process at Rev. 03 — 27 April 2009 PCA9533 2 4-bit I C-bus LED dimmer ...

Page 15

... NXP Semiconductors 11. Dynamic characteristics Table 14. Dynamic characteristics Symbol Parameter f SCL clock frequency SCL t bus free time between a STOP and BUF START condition t hold time (repeated) START condition HD;STA t set-up time for a repeated START SU;STA condition t set-up time for STOP condition SU;STO ...

Page 16

... NXP Semiconductors SDA t BUF t LOW SCL t HD;STA P S Fig 19. Definition of timing protocol SCL SDA Fig 20. I 12. Test information Fig 21. Test circuitry for switching times PCA9533_3 Product data sheet HD;DAT HIGH SU;DAT START bit 7 bit 6 condition MSB (A6) (S) (A7 SU;STA LOW HIGH ...

Page 17

... NXP Semiconductors 13. Package outline SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 18

... NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 19

... NXP Semiconductors 14. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...

Page 20

... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 15.4 Reflow soldering Key characteristics in reflow soldering are: • ...

Page 21

... NXP Semiconductors Fig 24. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 16. Abbreviations Table 17. Acronym ACPI CDM DSP DUT ESD GPIO HBM 2 I C-bus LED MCU ...

Page 22

... Release date PCA9533_3 20090427 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Figure 11 “Write to • Figure 13 “Read input port – ...

Page 23

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 24

... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 6.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2.1 Control register definition . . . . . . . . . . . . . . . . . 5 6.3 Register descriptions . . . . . . . . . . . . . . . . . . . . 5 6.3.1 INPUT - Input register ...

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