LM3424MH/NOPB National Semiconductor, LM3424MH/NOPB Datasheet - Page 17

• Manufacturer Part Number: LM3424MH/NOPB
• Description: IC LED DVR BUCK/BOOST 20-TSSOP
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: High Power, Constant Currentr

Specifications of LM3424MH/NOPB

• Constant Current: Yes
• Topology: Flyback, PWM, SEPIC, Step-Down (Buck), Step-Up (Boost)
• Number Of Outputs: 1
• Internal Driver: No
• Type - Primary: Automotive
• Type - Secondary: High Brightness LED (HBLED)
• Frequency: 2MHz
• Voltage - Supply: 4.5 V ~ 75 V
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP Exposed Pad, 20-eTSSOP, 20-HTSSOP
• Operating Temperature: -40°C ~ 125°C
• Current - Output / Channel: 1A
• Internal Switch(s): Yes
• Efficiency: 96%
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Other names: LM3424MH

To mitigate this problem, a compensator should be designed
to give adequate phase margin (above 45°) at the crossover
frequency. A simple compensator using a single capacitor at
the COMP pin (C
which will ensure adequate phase margin if placed low
enough. At high duty cycles (as shown in
zero places extreme limits on the achievable bandwidth with
this type of compensation. However, because an LED driver
is essentially free of output transients (except catastrophic
failures open or short), the dominant pole approach, even with
reduced bandwidth, is usually the best approach. The domi-
nant compensation pole (ω
output resistance (R
It may also be necessary to add one final pole at least one
decade above the crossover frequency to attenuate switching
noise and, in some cases, provide better gain margin. This
pole can be placed across R
resistor at the same time.
sation is physically implemented in the system.
The high frequency pole (ω
The total system transfer function becomes:
The resulting compensated loop gain frequency response
shown in
phase margin (above 45°) if the dominant compensation pole
is placed low enough, ensuring stability:
FIGURE 11. Compensated Loop Gain Frequency
Figure 11
CMP
O
indicates that the system has adequate
) will add a dominant pole to the system,
) of the error amplifier (typically 5 MΩ):
Response
Figure 10
P2
P3
SNS
) is determined by C
) can be calculated:
to filter the ESL of the sense
shows how the compen-
Figure
9), the RHP
CMP
300857a4
and the
17
START-UP REGULATOR and SOFT-START
The LM3424 includes a high voltage, low dropout bias regu-
lator. When power is applied, the regulator is enabled and
sources current into an external capacitor (C
to the V
V
ulator is monitored by an internal UVLO circuit that protects
the device from attempting to operate with insufficient supply
voltage and the supply is also internally current limited.
The LM3424 also has programmable soft-start, set by an ex-
ternal capacitor (C
to affect start-up, C
converter does not start in foldback mode.
the typical start-up waveforms for the LM3424 assuming
C
First, C
(~4.2V). The C
Assuming there is no C
C
(t
Once C
the LED current is in regulation. The C
can be roughly estimated as:
If C
itor will only charge to 0.7V over a smaller C
(t
CMP
CMP-SS
CC
REF
CMP
SS
regulator is 2.2 µF to 3.3 µF. The output of the V
) which can be estimated as:
> C
, C
is greater than 40% of C
CC
CMP
) which can be estimated as:
BYP
CMP
NTC
pin. The recommended bypass capacitance for the
= 0.9V, the part starts switching to charge C
is charged to be above V
.
FIGURE 12. Start-up Waveforms
is then charged to 0.9V over the charging time
VCC
SS
REF
charging time (t
), connected from SS to GND. For C
> C
SS
NTC
or if C
must be maintained so that the
CMP
, the compensation capac-
VCC
SS
) can be estimated as:
is less than 40% of
O
CC
charging time (t
CMP
Figure 12
UVLO threshold
BYP
30085761
charging time
) connected
www.national.com
CC
shows
O
until
reg-
CO
SS
)