LT1162CSW#PBF Linear Technology, LT1162CSW#PBF Datasheet - Page 6
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LT1162CSW#PBF
Manufacturer Part Number
LT1162CSW#PBF
Description
IC PWR MOSFET DRIVER NCH 24SOIC
Manufacturer
Linear Technology
Datasheet
1.LT1160CSPBF.pdf
(16 pages)
Specifications of LT1162CSW#PBF
Configuration
Half Bridge
Input Type
Non-Inverting
Delay Time
250ns
Current - Peak
1.5A
Number Of Configurations
2
Number Of Outputs
4
High Side Voltage - Max (bootstrap)
60V
Voltage - Supply
10 V ~ 15 V
Operating Temperature
25°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
24-SOIC (7.5mm Width)
Number Of Drivers
4
Driver Configuration
Non-Inverting
Driver Type
High Side/Low Side
Input Logic Level
CMOS/TTL
Rise Time
200ns
Fall Time
140ns
Operating Supply Voltage (max)
15V
Peak Output Current
1.5A
Operating Supply Voltage (min)
10V
Operating Supply Voltage (typ)
12V
Turn Off Delay Time
600fs
Turn On Delay Time (max)
500ps
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
24
Package Type
SOIC W
Device Type
MOSFET
Module Configuration
Half / Full Bridge
Input Delay
180ns
Output Delay
180ns
Supply Voltage Range
10V To 15V
Driver Case Style
SOIC
No. Of Pins
24
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
LT1160
SV
to the signal ground Pin 5.
IN TOP (Pin 2): Top Driver Input. Pin 2 is disabled when Pin
3 is high. A 3k input resistor followed by a 5V internal
clamp prevents saturation of the input transistors.
IN BOTTOM (Pin 3): Bottom Driver Input. Pin 3 is disabled
when Pin 2 is high. A 3k input resistor followed by a 5V
internal clamp prevents saturation of the input transistors.
UV OUT (Pin 4): Undervoltage Output. Open collector NPN
output which turns on when V
undervoltage threshold.
SGND (Pin 5): Small Signal Ground. Must be routed
separately from other grounds to the system ground.
PGND (Pin 6): Bottom Driver Power Ground. Connects to
source of bottom N-channel MOSFET.
B GATE FB (Pin 8): Bottom Gate Feedback. Must connect
directly to the bottom power MOSFET gate. The top
MOSFET turn-on is inhibited until Pin 8 has discharged to
below 2.5V.
B GATE DR (Pin 9): Bottom Gate Drive. The high current
drive point for the bottom MOSFET. When a gate resistor
is used it is inserted between Pin 9 and the gate of the
MOSFET.
PV
the same supply as Pin 1.
T SOURCE (Pin 11): Top Driver Return. Connects to the
top MOSFET source and the low side of the bootstrap
capacitor.
T GATE FB (Pin 12): Top Gate Feedback. Must connect
directly to the top power MOSFET gate. The bottom
MOSFET turn-on is inhibited until V
to below 2.9V.
T GATE DR (Pin 13): Top Gate Drive. The high current drive
point for the top MOSFET. When a gate resistor is used it
is inserted between Pin 13 and the gate of the MOSFET.
BOOST (Pin 14): Top Driver Supply. Connects to the high
side of the bootstrap capacitor.
LT1160/LT1162
PIN
6
+
+
U
(Pin 1): Main Signal Supply. Must be closely decoupled
(Pin 10): Bottom Driver Supply. Must be connected to
FUNCTIONS
U
U
12
+
– V
drops below the
11
has discharged
LT1162
SV
decoupled to ground Pins 5 and 11.
IN TOP (Pins 2, 8): Top Driver Input. The Input Top is
disabled when the Input Bottom is high. A 3k input resistor
followed by a 5V internal clamp prevents saturation of the
input transistors.
IN BOTTOM (Pins 3, 9): Bottom Driver Input. The Input
Bottom is disabled when the Input Top is high. A 3k input
resistor followed by a 5V internal clamp prevents satura-
tion of the input transistors.
UV OUT (Pins 4, 10): Undervoltage Output. Open collector
NPN output which turns on when V
undervoltage threshold.
GND (Pins 5, 11): Ground Connection.
B GATE FB (Pins 6, 12): Bottom Gate Feedback. Must
connect directly to the bottom power MOSFET gate. The
top MOSFET turn-on is inhibited until Bottom Gate Feed-
back pins have discharged to below 2.5V.
B GATE DR (Pins 13, 19): Bottom Gate Drive. The high
current drive point for the bottom MOSFET. When a gate
resistor is used it is inserted between the Bottom Gate
Drive pin and the gate of the MOSFET.
PV
nected to the same supply as Pins 1 and 7.
T SOURCE (Pins 15, 21): Top Driver Return. Connects to
the top MOSFET source and the low side of the bootstrap
capacitor.
T GATE FB (Pins 16, 22): Top Gate Feedback. Must
connect directly to the top power MOSFET gate. The
bottom MOSFET turn-on is inhibited until V
has discharged to below 2.9V.
T GATE DR (Pins 17, 23): Top Gate Drive. The high current
drive point for the top MOSFET. When a gate resistor is
used it is inserted between the Top Gate Drive pin and the
gate of the MOSFET.
BOOST (Pins 18, 24): Top Driver Supply. Connects to the
high side of the bootstrap capacitor.
+
+
(Pins 14, 20): Bottom Driver Supply. Must be con-
(Pins 1, 7): Main Signal Supply. Must be closely
+
drops below the
TGF
– V
TSOURCE
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