LT1162CSW#PBF Linear Technology, LT1162CSW#PBF Datasheet - Page 8

• Manufacturer Part Number: LT1162CSW#PBF
• Description: IC PWR MOSFET DRIVER NCH 24SOIC
• Manufacturer: Linear Technology

Specifications of LT1162CSW#PBF

• Configuration: Half Bridge
• Input Type: Non-Inverting
• Delay Time: 250ns
• Current - Peak: 1.5A
• Number Of Configurations: 2
• Number Of Outputs: 4
• High Side Voltage - Max (bootstrap): 60V
• Voltage - Supply: 10 V ~ 15 V
• Operating Temperature: 25°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Number Of Drivers: 4
• Driver Configuration: Non-Inverting
• Driver Type: High Side/Low Side
• Input Logic Level: CMOS/TTL
• Rise Time: 200ns
• Fall Time: 140ns
• Operating Supply Voltage (max): 15V
• Peak Output Current: 1.5A
• Operating Supply Voltage (min): 10V
• Operating Supply Voltage (typ): 12V
• Turn Off Delay Time: 600fs
• Turn On Delay Time (max): 500ps
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 24
• Package Type: SOIC W
• Device Type: MOSFET
• Module Configuration: Half / Full Bridge
• Input Delay: 180ns
• Output Delay: 180ns
• Supply Voltage Range: 10V To 15V
• Driver Case Style: SOIC
• No. Of Pins: 24
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OPERATIO
LT1160/LT1162
The LT1160 (or 1/2 LT1162) incorporates two indepen-
dent driver channels with separate inputs and outputs. The
inputs are TTL/CMOS compatible; they can withstand
input voltages as high as V
regulated and has 300mV of hysteresis. Both channels are
noninverting drivers. The internal logic prevents both
outputs from simultaneously turning on under any input
conditions. When both inputs are high both outputs are
actively held low.
The floating supply for the top driver is provided by a
bootstrap capacitor between the Boost pin and the Top
Source pin. This capacitor is recharged each time the
negative plate goes low in PWM operation.
The undervoltage detection circuit disables both channels
when V
TI I G DIAGRA
8
IN BOTTOM
TOP GATE
BOTTOM
W
DRIVER
DRIVER
IN TOP
GATE
U
+
0.8V
0.8V
12V
12V
2V
2V
0V
0V
is below the undervoltage trip point. A separate
t
D1
U
(Refer to Functional Diagram)
t
r
2V
10V
+
W
. The 1.4V input threshold is
t
D3
t
f
t
D4
t
D2
UV detect block disables the high side channel when
V
point.
The top and bottom gate drivers in the LT1160 each utilize
two gate connections: 1) a gate drive pin, which provides
the turn on and turn off currents through an optional series
gate resistor, and 2) a gate feedback pin which connects
directly to the gate to monitor the gate-to-source voltage.
Whenever there is an input transition to command the
outputs to change states, the LT1160 follows a logical
sequence to turn off one MOSFET and turn on the other.
First, turn-off is initiated, then V
decreased below the turn-off threshold, and finally the
other gate is turned on.
BOOST
t
D1
– V
t
r
2V
TSOURCE
10V
t
D3
is below its own undervoltage trip
t
f
t
D4
GS
is monitored until it has
t
D2
1160/62 TD
11602fb