HCPL-316J Avago Technologies US Inc., HCPL-316J Datasheet - Page 33
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HCPL-316J
Manufacturer Part Number
HCPL-316J
Description
OPTOCOUPLER GATE DRV 2A 16-SOIC
Manufacturer
Avago Technologies US Inc.
Datasheet
1.HCPL-316J-500E.pdf
(33 pages)
Specifications of HCPL-316J
Configuration
High-Side
Input Type
Differential
Delay Time
300ns
Current - Peak
2.5A
Number Of Configurations
1
Number Of Outputs
1
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.300", 7.5mm Width)
No. Of Channels
1
Isolation Voltage
3.75kV
Optocoupler Output Type
Gate Drive
Input Current
22mA
Output Voltage
30V
Opto Case Style
SOIC
No. Of Pins
16
Propagation Delay Low-high
0.5µs
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
High Side Voltage - Max (bootstrap)
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
Other names
516-1130-5
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Figure 80. Minimum LED Skew for Zero Dead Time.
For product information and a complete list of distributors, please go to our website:
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. Obsoletes AV01-0579EN
AV02-0717EN - March 28, 2011
System Considerations
Propagation Delay Difference (PDD)
The HCPL-316J includes a Propagation Delay Difference
(PDD) specification intended to help designers minimize
“dead time” in their power inverter designs. Dead time
is the time period during which both the high and low
side power transistors (Q1 and Q2 in Figure 62) are off.
Any overlap in Q1 and Q2 conduction will result in large
currents flowing through the power devices between
the high and low voltage motor rails, a potentially cata-
strophic condi tion that must be prevented.
To minimize dead time in a given design, the turn-on of
the HCPL-316J driving Q2 should be delayed (relative to
the turn-off of the HCPL-316J driving Q1) so that under
worst-case conditions, transistor Q1 has just turned off
when transistor Q2 turns on, as shown in Figure 80. The
amount of delay necessary to achieve this condition is
equal to the maxi mum value of the propagation delay
difference specification, PDD
be 400 ns over the operating temperature range of -40°C
to 100°C.
V
V
V
V
OUT1
OUT2
*PDD = PROPAGATION DELAY
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
IN+1
IN+2
PDD* MAX = (t
t
PHL MAX
Q2 OFF
Q1 ON
t
PLH MIN
PHL
MAX
- t
PLH
, which is specified to
)
MAX
= t
Q1 OFF
Q2 ON
PHL MAX
- t
PLH MIN
www.avagotech.com
Figure 81. Waveforms for Dead Time Calculation.
Delaying the HCPL-316J turn-on signals by the maximum
propaga tion delay difference ensures that the minimum
dead time is zero, but it does not tell a designer what the
maximum dead time will be. The maximum dead time is
equivalent to the difference between the maximum and
minimum propagation delay difference specifications
as shown in Figure 81. The maximum dead time for the
HCPL-316J is 800 ns (= 400 ns - (-400 ns)) over an operat-
ing temperature range of -40°C to 100°C.
Note that the propagation delays used to calculate PDD
and dead time are taken at equal tempera tures and test
conditions since the optocouplers under consider a tion
are typically mounted in close proximity to each other
and are switching identical IGBTs.
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
V
V
V
V
OUT1
OUT2
IN+1
IN+2
(t
PHL-
Q2 OFF
Q1 ON
t
t
PHL MIN
PHL MAX
t
PLH
)
MAX
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (t
= (t
= PDD*
= PDD*
PHL MAX
PHL MAX
t
PLH MIN
MAX
t
PLH MAX
MAX
- t
- t
– PDD*
PHL MIN
PLH MIN
MIN
) + (t
) – (t
PLH MAX
PHL MIN
Q1 OFF
Q2 ON
- t
- t
PLH MAX
PLH MIN
)
)