ISL6208CBZ Intersil, ISL6208CBZ Datasheet - Page 9

• Manufacturer Part Number: ISL6208CBZ
• Description: IC MOSFET DRVR SYNC BUCK 8-SOIC
• Manufacturer: Intersil

Specifications of ISL6208CBZ

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 20ns
• Current - Peak: 2A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 33V
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

where f
and V
and Q
MOSFET selection and any external capacitance added to
the gate pins. The lV
of the driver and is typically negligible.
Layout Considerations
Reducing Phase Ring
The parasitic inductances of the PCB and power devices
(both upper and lower FETs) could cause increased PHASE
ringing, which may lead to voltages that exceed the absolute
maximum rating of the devices. When PHASE rings below
ground, the negative voltage could add charge to the
bootstrap capacitor through the internal bootstrap diode.
Under worst-case conditions, the added charge could
overstress the BOOT and/or PHASE pins. To prevent this
1000
900
800
700
600
500
400
300
200
100
L
L
FIGURE 9. POWER DISSIPATION vs FREQUENCY
0
sw
represent the upper and lower gate rail voltage. Q
is the upper and lower gate charge determined by
0
Q
Q
is the switching frequency of the PWM signal. V
U
L
200
= 200nC
=100nC
400
CC
600
Q
Q
V
L
FREQUENCY (kHz)
U
CC
= 100nC
800 1000 1200 1400 1600 1800 2000
= 50nC
product is the quiescent power
9
Q
Q
Q
Q
U
L
U
L
= 50nC
= 50nC
=50nC
= 20nC
U
U
ISL6208
from happening, the user should perform a careful layout
inspection to reduce trace inductances, and select low lead
inductance MOSFETs and drivers. D
packaged MOSFETs have high parasitic lead inductances,
as opposed to SOIC-8. If higher inductance MOSFETs must
be used, a Schottky diode is recommended across the lower
MOSFET to clamp negative PHASE ring.
A good layout would help reduce the ringing on the phase
and gate nodes significantly:
• Avoid using vias for decoupling components where
• All power traces (UGATE, PHASE, LGATE, GND, VCC)
• Keep the SOURCE of the upper FET as close as thermally
• Keep the connection in between the SOURCE of lower
• Input capacitors should be placed as close to the DRAIN
Note: Refer to Intersil Tech Brief TB447 for more information.
Thermal Management
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal
pad of the QFN part to the power ground with multiple vias,
or placing a low noise copper plane underneath the SOIC
part is recommended. This heat spreading allows the part to
achieve its full thermal potential.
possible, especially in the BOOT-to-PHASE path. Little or
no use of vias for VCC and GND is also recommended.
Decoupling loops should be short.
should be short and wide, and avoid using vias. If vias
must be used, two or more vias per layer transition is
recommended.
possible to the DRAIN of the lower FET.
FET and power ground wide and short.
of the upper FET and the SOURCE of the lower FET as
thermally possible.
2
PAK and DPAK
August 7, 2008
FN9115.3