ISL6622ACBZ Intersil, ISL6622ACBZ Datasheet - Page 6

• Manufacturer Part Number: ISL6622ACBZ
• Description: IC MOSFET DRVR SYNC BUCK 8-SOIC
• Manufacturer: Intersil

Specifications of ISL6622ACBZ

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 20ns
• Current - Peak: 1.25A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 36V
• Voltage - Supply: 6.8 V ~ 13.2 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Description
Operation and Adaptive Shoot-through Protection
Designed for high speed switching, the ISL6622A MOSFET
driver controls both high-side and low-side N-Channel FETs
from one externally provided PWM signal.
A rising transition on PWM initiates the turn-off of the lower
MOSFET (see Figure 1). After a short propagation delay
[t
provided in the “Electrical Specifications” on page 5. Following
a 25ns blanking period, adaptive shoot-through circuitry
monitors the LGATE voltage and turns on the upper gate
following a short delay time [t
drops below ~1.75V. The upper gate drive then begins to rise
[t
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
gate begins to fall [t
monitors the UGATE-PHASE voltage and turns on the lower
MOSFET a short delay time [t
MOSFET’s PHASE voltage drops below +0.8V or 40ns after
the upper MOSFET’s gate voltage [UGATE-PHASE] drops
below ~1.75V. The lower gate then rises [t
lower MOSFET. These methods prevent both the lower and
upper MOSFETs from conducting simultaneously
(shoot-through), while adapting the dead-time to the gate
charge characteristics of the MOSFETs being used.
This driver is optimized for voltage regulators with large step
down ratio. The lower MOSFET is usually sized larger
compared to the upper MOSFET because the lower MOSFET
conducts for a longer time during a switching period. The
lower gate driver is therefore sized much larger to meet this
application requirement. The 0.8Ω ON-resistance and 3A sink
current capability enable the lower gate driver to absorb the
current injected into the lower gate through the drain-to-gate
capacitor of the lower MOSFET and help prevent
PDLL
RU
] and the upper MOSFET turns on.
PWM
UGATE
LGATE
], the lower gate begins to fall. Typical fall time [t
t
PDLL
FU
PDLU
]. The adaptive shoot-through circuitry
] is encountered before the upper
t
PDHU
FL
PDHL
6
t
PDHU
] after the LGATE voltage
] after the upper
t
RU
t
PDHL
RL
], turning on the
FIGURE 1. TIMING DIAGRAM
t
RL
t
PDLU
FL
t
] is
FU
ISL6622A
1.5V < PWM < 3.2V
shoot-through caused by the self turn-on of the lower
MOSFET due to high dV/dt of the switching node.
Advanced PWM Protocol (Patent Pending)
The advanced PWM protocol of ISL6622A is specifically
designed to work with Intersil VR11.1 controllers. When
ISL6622A detects a PSI protocol sent by an Intersil VR11.1
controller, it turns on diode emulation operation; otherwise, it
remains in normal CCM PWM mode.
Another unique feature of ISL6622A and other Intersil
drivers is the addition of a three-state shutdown window to
the PWM input. If the PWM signal enters and remains within
the shutdown window for a set holdoff time, the driver
outputs are disabled and both MOSFET gates are pulled and
held low. The shutdown state is removed when the PWM
signal moves outside the shutdown window. Otherwise, the
PWM rising and falling thresholds outlined in the “Electrical
Specifications” on page 4 determine when the lower and
upper gates are enabled. This feature helps prevent a
negative transient on the output voltage when the output is
shut down, eliminating the Schottky diode that is used in
some systems for protecting the load from reversed output
voltage events.
Note that the LGATE will not turn off until the diode
emulation minimum LGATE ON-time of 350ns is expired for
a PWM low to tri-level (2.5V) transition.
Power-On Reset (POR) Function
During initial start-up, the VCC voltage rise is monitored.
Once the rising VCC voltage exceeds rising POR threshold,
operation of the driver is enabled and the PWM input signal
takes control of the gate drives. If VCC drops below the
falling threshold, operation of the driver is disabled.
Pre-POR Overvoltage Protection
While VCC is below its POR level, the upper gate is held low
and LGATE is connected to the PHASE pin via an internal
10kΩ (typically) resistor. By connecting the PHASE node to the
gate of the low side MOSFET, the driver offers some passive
t
TSSHD
t
PDTS
t
UG_OFF_DB
1.0V< PWM < 2.6V
March 19, 2009
t
PDTS
FN6601.2