A3936SED Allegro Microsystems Inc, A3936SED Datasheet - Page 7

• Manufacturer Part Number: A3936SED
• Description: IC MOTOR DRIVER PWM 3PH 44-PLCC
• Manufacturer: Allegro Microsystems Inc

Specifications of A3936SED

• Applications: DC Motor Driver, Brushless (BLDC), 3 Phase
• Number Of Outputs: 1
• Current - Output: ±3A
• Voltage - Load: 9 V ~ 50 V
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Operating Current: 10mA
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

VREG.
μF capacitor to ground. This supply voltage is used to run
the sink side DMOS outputs. VREG is internally monitored
and in the case of a fault condition, the outputs of the device
are disabled.
Charge Pump.
supply above VBB to drive the source side DMOS gates. A
0.22 uF ceramic monolithic capacitor should be connected
between CP
ceramic monolithic capacitor should be connected between
V
DMOS devices. The V
and in the case of a fault condition the outputs of the device
are disabled.
Shutdown.
junction temperature, or low voltage on V
outputs of the device are disabled until the fault condition is
removed. At power up, and in the event of low V
UVLO circuit disables the drivers.
Current Regulation.
internal fixed off time PWM control circuit. When the
outputs of the DMOS H-bridge are turned on, current
increases in the motor winding until it reaches a value given
by:
At the trip point, the sense comparator resets the source
enable latch, turning off the source driver. At this point,
load inductance causes the current to recirculate for the
fixed off time period. The current path during recirculation
is determined by the configuration of slow/mixed decay
mode and the synchronous rectification control setting.
Enable Logic.
external PWM. ENABLE high turns ON the selected sink-
source pair, enable low switches off the appropriate drivers
and the load current decays. If the ENABLE pin is held
high, the current will rise until it reaches the level set by the
internal current control circuit.
A3936
CP
ENABLE
and VBB to act as a reservoir to run the high side
0
1
I
The VREG pin should be decoupled with a 0.22
TRIP
1
and CP
= V
In the event of a fault due to excessive
REF
Chopped
Outputs
The Enable input terminal allows
Source
The Charge Pump is used to generate a
2
/(10*R
ON
for pumping purposes. A 0.22 uF
CP
Voltage is internally monitored
Load current is regulated by an
SENSE
)
CP
or V
Functional Description
REG
DD
, the
DMOS Three-Phase PWM Motor Driver
, the
Extmode Logic.
control, the EXTMODE input determines the current path
during the chopped cycle. With EXTMODE set low, fast
decay mode, both the source and sink drivers are chopped
OFF during the decay time (ENABLE=0). With
EXTMODE high, slow decay mode, only the source driver
turns off during the current decay time.
Sleep Mode.
the device into a minimum current draw mode. When
asserted low, all circuits are disabled.
Fixed Off-Time.
96 counts of the internal oscillator, typically 24 μs with
4Mhz oscillator.
Internal Current Control Mode.
and PFD2 determine the current decay method after an
overcurrent event is detected at sense input. In slow decay
mode both sink side drivers are turned on for the fixed off
time period. Mixed decay mode starts out in fast decay
mode for the selected percentage of the fixed off time, and
then is followed by slow decay for the rest of the period.
EXTMODE
0
1
PFD2
0
0
1
1
The input pin SLEEP is dedicated to put
Decay
PFD1
Slow
Fast
The 3936 is set for a fixed off time of
When using external PWM current
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
0
1
0
1
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
% t
100
15
48
0
OFF
Input pins PFD1
Decay
Mixed
Mixed
Slow
Fast
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