L6562D STMicroelectronics, L6562D Datasheet - Page 8
![IC PFC CTRLR TRANSITION 8SOIC](/photos/1/38/13851/497-8-soic_sml.jpg)
L6562D
Manufacturer Part Number
L6562D
Description
IC PFC CTRLR TRANSITION 8SOIC
Manufacturer
STMicroelectronics
Datasheet
1.L6562N.pdf
(16 pages)
Specifications of L6562D
Mode
Discontinuous (Transition)
Frequency - Switching
1MHz
Current - Startup
40µA
Voltage - Supply
10.3 V ~ 22 V
Operating Temperature
-25°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
For Use With
497-8406 - BOARD STF20NM50FD/STF7LITE39BF2497-8249 - BOARD EVAL FOR L6562AX497-8248 - BOARD EVAL FOR L6562AX
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
L6562D
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
L6562DTR
Manufacturer:
ST
Quantity:
5 000
L6562
Figure 20. Gate-drive clamp vs. T
4
4.1 Overvoltage protection
Under steady-state conditions, the voltage control loop keeps the output voltage Vo of a PFC pre-regulator
close to its nominal value, set by the resistors R1 and R2 of the output divider. Neglecting ripple compo-
nents, the current through R1, I
the error amplifier is internally referenced at 2.5V, also the voltage at pin INV will be 2.5V, then:
If the output voltage experiences an abrupt change ∆Vo > 0 due to a load drop, the voltage at pin INV will
be kept at 2.5V by the local feedback of the error amplifier, a network connected between pins INV and
COMP that introduces a long time constant to achieve high PF (this is why ∆Vo can be large). As a result,
the current through R2 will remain equal to 2.5/R2 but that through R1 will become:
The difference current ∆I
ter the error amplifier output (pin COMP). This current is monitored inside the L6562 and if it reaches about
37 µA the output voltage of the multiplier is forced to decrease, thus smoothly reducing the energy deliv-
ered to the output. As the current exceeds 40 µA, the OVP is triggered (Dynamic OVP): the gate-drive is
forced low to switch off the external power transistor and the IC put in an idle state. This condition is main-
tained until the current falls below approximately 10 µA, which re-enables the internal starter and allows
switching to restart. The output ∆Vo that is able to trigger the Dynamic OVP function is then:
An important advantage of this technique is that the OV level can be set independently of the regulated
output voltage: the latter depends on the ratio of R1 to R2, the former on the individual value of R1. Another
advantage is the precision: the tolerance of the detection current is 12%, that is 12% tolerance on ∆Vo.
Since ∆Vo << Vo, the tolerance on the absolute value will be proportionally reduced.
Example: Vo = 400 V, ∆Vo = 40 V. Then: R1=40V/40µA=1MΩ; R2=1MΩ·2.5/(400-2.5)=6.289kΩ. The tol-
erance on the OVP level due to the L6562 will be 40·0.12=4.8V, that is 1.2% of the regulated value.
8/16
Vpin7
(V)
Application Information
clamp
15
14
13
12
11
10
-50
0
R1
Tj (°C)
=I'
50
R1
R1
-I
R2
, equals that through R2, I
=I'
j
Vcc = 20 V
100
I
R1
R2
-I
I'
∆
R1
R1
=
Vo
=∆Vo/R1 will flow through the compensation network and en-
2.5
------- -
R2
=
150
=
Vo 2.5
--------------------------------------- -
=
R1 40 10
I
–
R1
⋅
R1
Figure 21. UVLO saturation vs. T
=
+
⋅
Vpin7
Vo 2.5
--------------------- -
(V)
∆
R2
Vo
R1
–
–
6
1.1
0.9
0.8
0.7
0.6
0.5
. Considering that the non-inverting input of
1
-50
.
.
.
0
Tj (°C)
50
Vcc = 0 V
j
100
150