LTC3589HUJ#PBF Linear Technology, LTC3589HUJ#PBF Datasheet - Page 28

• Manufacturer Part Number: LTC3589HUJ#PBF
• Description: IC DC/DC CONV 8-OUTPUT 40QFN
• Manufacturer: Linear Technology

Specifications of LTC3589HUJ#PBF

• Applications: Handheld/Mobile Devices
• Current - Supply: 8µA
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: *
• Primary Input Voltage: 5.5V
• No. Of Outputs: 8
• Output Voltage: 5V
• Output Current: 1.6A
• No. Of Pins: 40
• Operating Temperature Range: -40°C To +150°C
• Msl: MSL 1 - Unlimited
• No. Of Ldo Regulators: 3
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC3589/LTC3589-1
OPERATION
A 0 or 1 to the odd bits of voltage change control register
VCCR selects DAC output voltages V1 or V2, respectively. A
slew of the DAC is initiated by writing a 1 to an even bit of
register VCCR. The DAC output will slew to either voltage,
V1 or V2, as selected by the odd bits of register VCCR.
Slew begins when the I
the end of the slewing operation the GO bits in command
register VCCR are cleared.
The slew rate for each regulator is set in the ramp rate
control register VRRCR. Each DAC has independent output
voltage registers, voltage register select, and slew rate and
start controls. The regulators do not have to be enabled
to change the DAC outputs.
The VSTB pin is used to set the DAC controlled output rails
to a low power standby condition. When VSTB is driven
HIGH, all four of the DAC references will immediately slew
to V2. To use VSTB to set the rails to standby voltage,
select V1 for normal rail voltages and V2 for standby rail
voltages. Drive VSTB high to immediately slew all the
DAC outputs to V2. When VSTB is driven LOW, the DAC
outputs will slew to V1.
The default power-up value of all the dynamic target voltage
registers is 11001 corresponding to a DAC output volt-
age of 0.675V. The DTV registers may be reprogrammed
prior to initiating a power-up sequence or at any time for
dynamic slewing.
When a step-down switching regulator output is slewing
down its mode is automatically switched to forced continu-
ous to enable the regulator to sink current. When LDO2 is
slewing down, a 2.5k pull-down is connected to its output.
Table 14 shows command register and feedback divider
settings to enable slewing step-down switching regulator 1
between 1.2V and 1V in 70μs. The voltage ramp rate
control register bits VRRCR[1:0] are set to 01 which
selects a ramp rate of 1.75mV/μs at the DAC output.
The slew rate at the regulator output is a function of the
feedback resistor divider gain. In this example, the slew
is equal to 1.75 • (1 + 301/499) = 2.8mV/μs. Therefore, a
slew of 200mV will take 70μs. To initiate a change from
1.2V to 1V write 11 to voltage change control register bits
VCCR[1:0]. VCCR[1] selects target register B1DTV2 to
set the regulator reference input to 0.625V. VCCR[0] set
28
2
C STOP condition is detected. At
to 1 initiates the dynamic slew to go to the new voltage.
To slew back to 1.2V write 01 to command register bits
VCCR[1:0].
Table 14. Dynamic Slewing Example for Step-Down Switching
Regulator 1
COMMAND
REGISTER
VRRCR[1:0]
VCCR[1]
B1DTV1[4:0]
B1DTV2[4:0]
PUSHBUTTON OPERATION
State Event Diagram
Figure 5 shows the LTC3589/LTC3589-1 pushbutton state
diagram. Upon the first power application to the LTC3589
V
ton into the power-down (PDN) state and initiates a one
second timer. The LTC3589 status pin RSTO is pulled low
until one second times out and the always-alive LDO1 is
indicating power good status. After the one second interval
the pushbutton circuit will transition to the power-off (POFF)
state. The LTC3589-1 powers on directly to the POFF state
bypassing the one second delay. Status pin RSTO will be
released high when LDO1 indicates power good status.
The pushbutton will not leave the POFF state and enter
the power-up state (PUP) until ON is held LOW for at least
400ms (PB400ms) or until PWR_ON is activated by the
PWR_ON pin. When the controller enters the PUP state
the open-drain WAKE pin releases HIGH. The WAKE pin
is typically used to enable the first regulator in a start-up
sequence. The pushbutton state will stay in PUP for five
seconds before transitioning to the power-on (PON) state.
Before leaving PUP , the PWR_ON pin must be brought
HIGH by the application to indicate that the system rails
are correct. If PWR_ON is not active at the end of five
seconds the pushbutton controller will continue directly
through PON to the power-down (PDN) state and pull the
WAKE pin down. Three events will cause the pushbutton
to leave the PON state: 1) lowering the PWR_ON pin, 2)
forcing a hard reset by holding the ON pin LOW for five
IN
pin an internal power-on reset circuit puts the pushbut-
V
OUT
10101
11111
01
=1.2V
0
V
OUT
10101
11111
01
=1V
1
Dynamic Slew Rate
Select DTV
Resistor Divider Shown
in Figure 3
R1 = 301kΩ
R2 = 499kΩ
3589fc