LTC3589HUJ#PBF Linear Technology, LTC3589HUJ#PBF Datasheet - Page 35

• Manufacturer Part Number: LTC3589HUJ#PBF
• Description: IC DC/DC CONV 8-OUTPUT 40QFN
• Manufacturer: Linear Technology

Specifications of LTC3589HUJ#PBF

• Applications: Handheld/Mobile Devices
• Current - Supply: 8µA
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: *
• Primary Input Voltage: 5.5V
• No. Of Outputs: 8
• Output Voltage: 5V
• Output Current: 1.6A
• No. Of Pins: 40
• Operating Temperature Range: -40°C To +150°C
• Msl: MSL 1 - Unlimited
• No. Of Ldo Regulators: 3
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OPERATION
pulls down the SDA line during the write acknowledge
clock pulse so that it is a stable LOW during the HIGH
period of this clock pulse.
I
The LTC3589/LTC3589-1 responds to factory programmed
read and write addresses. The write address is 0x68. The
read address is 0x69. The least significant bit of the address
byte, known as the read/write bit, is 0 when writing data
to the LTC3589/LTC3589-1 and 1 when reading from it.
I
The LTC3589/LTC3589-1 has 14 command registers for
control inputs. They are accessed by the I
sub-addressed writing system.
Each write cycle of the LTC3589/LTC3589-1 consists of a
series of three or more bytes beginning with the LTC3589/
LTC3589-1 write address. The second byte is the sub
address of the command register being written to. The
sub address is a pointer to the register where the data
in the third byte will be stored. The third byte is the data
to be written to the just-received sub address. Continue
alternating sub address and data bytes to write multiple
registers in a single START sequence.
I
The master initiates communication with the LTC3589/
LTC3589-1 with a START condition and the LTC3589/
LTC3589-1write address. If the address matches that of
the LTC3589/LTC3589-1, the LTC3589/LTC3589-1 returns
an acknowledge pulse. The master should then deliver the
sub address. Again the LTC3589/LTC3589-1 acknowledges
and the cycle is repeated for the data byte. The data byte
is transferred to an internal holding latch upon the return
2
2
2
SDA
SCL
C Slave Address
C Sub-Addressed Writing
C Bus Write Operation
START
0
0
1
1
1
2
1
1
3
ADDRESS
0
0
4
1
1
5
0
0
6
0
0
7
WR
0
8
ACK
9
S7 S6
1
Figure 20. LTC3589 I
2
S5
3
SUB ADDRESS
S4
2
4
C port via a
S3
5
S2 S1 S0
6
7
8
2
C Serial Port Read Pattern
ACK
9
START
of its acknowledge by the LTC3589/LTC3589-1. Continue
writing sub address and data pairs into the holding latches.
Addressing the LTC3589LTC3589-1 is not required for each
sub address and data pair. If desired a REPEAT-START
condition may be initiated by the master where another
device on the I
remembers the valid data it has received. Once all the
devices on the I
data and a global STOP has been sent, the LTC3589/
LTC3589-1 will update its command latches with the data
it has received.
I
The LTC3589/LTC3589-1 I
address reading of the I
Before reading a register, the registers sub address must be
written. Send a START condition followed by the LTC3589/
LTC3589-1 write address followed by the sub address of
the register to be read. The sub address is now stored as
a pointer to the register. Send a REPEAT-START condition
followed by the LTC3589/LTC3589-1 read address. Follow-
ing the acknowledgment of its read address the LTC3589/
LTC3589-1 returns one bit of information for each of the
next 8 clock cycles. A STOP condition is not required for
the read operation. The read sub address is stored until
a new sub address is written.
Verify the data written to the internal data hold latches
prior to committing date to the command registers by
reading back the data before sending a STOP condition.
Continuously poll a register by repeatedly sending a
START condition followed by the LTC3589/LTC3589-1
read address, and then clocking the data out after the read
address acknowledge.
2
C Sub-Addressed Reading
0
0
1
1
1
2
1
1
3
ADDRESS
0
0
4
2
C bus is addressed. The LTC3589/LTC3589-1
1
1
5
LTC3589/LTC3589-1
2
0
0
6
C have been addressed and sent valid
0
0
7
RD
1
8
2
C command and status registers.
ACK
9
2
C interface supports random
R7 R6
1
2
R5
3
R4
4
DATA
R3
5
R2 R1 R0
6
7
8
35
ACK
9
3589 F20
3589fc
STOP