IR3527MTRPBF International Rectifier, IR3527MTRPBF Datasheet
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IR3527MTRPBF
Specifications of IR3527MTRPBF
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IR3527MTRPBF Summary of contents
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DESCRIPTION The IR3527 Dual Phase IC combined with an IR XPhase3 way to implement multiphase power solutions. The Control IC provides overall system control and interfaces with any number of IR3527 Phase ICs which each drive and monitor 2 phases ...
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... ORDERING INFORMATION Part Number IR3527MTRPBF * IR3527MPBF * Samples only PIN DESCRIPTION PIN# PIN PIN DESCRIPTION SYMBOL 1 CSIN1+ Phase1 current sense amplifier non-inverting input and input to debug comparator 2 EAIN PWM comparator input from the error amplifier output of Control IC. Body Braking mode is initiated if the voltage on this pin is less than V(DACIN) threshold. ...
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GATEH2 Phase2 High-side driver output and input to GATEL2 non-overlap comparator. 20 SW2 Return for Phase2 high-side driver and reference for GATEL2 non-overlap comparator. 21 VCC Supply for internal IC circuits. Input to PWM feed-forward. 22 CSIN2+ Phase2 current ...
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GATEH2 20 SW2 21 VCC 22 CSIN2+ 23 CSIN2- 24 CSIN1- 25 LGND Note: 1. Maximum GATEHx – SWx = 8V 2. Maximum BOOSTx – GATEHx = 8V RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN 8.0V V 28V, ...
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PARAMETER GATELx low to GATEHx BOOSTx = VCCLx = 7V, SWx = PGND = 0V, high delay measure time from GATELx falling GATEHx rising to 1V GATEHx low to GATELx BOOSTx = VCCLx = 7V, SWx = ...
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Current Sense Amplifiers CSINx+/- Bias Current CSINx+/- Bias Current Note 1 Mismatch Input Offset Voltage CSINx+ = CSINx- = DACIN. Measure input referred offset from DACIN Gain 0.5V Unity Gain Bandwidth C(ISHARE)=10pF. Measure at ISHARE. Note 1 Slew Rate Note ...
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PARAMETER PSI Comparator Rising Threshold Voltage Falling Threshold Voltage Hysteresis Resistance Floating Voltage General VCC Supply Current VCC Supply Current VCCLx Supply Current BOOSTx Supply Current DACIN Bias Current SW Floating Voltage Note 1: Guaranteed by design, but not tested ...
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GATE DRIVE VOLTAGE CONTROL IC CLOCK GENERATOR CLKOUT PHSOUT PHSIN REMOTE SENSE + AMPLIFIER - VO VDAC LGND ERROR AMPLIFIER VDAC EAOUT + - RCOMP CCOMP1 RFB1 RFB CCOMP FB CFB RVSETPT RDRP1 VSETPT RDRP IVSETPT IROSC VDRP CDRP AMP ...
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PWM Operation The PWM comparator is located in the phase IC. Upon receiving the falling edge of a clock pulse, the PWM latch is sets and the PWM ramp voltage begins to increase. In conjunction, the low side driver is ...
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Since the voltage drop in the body diode is often comparable to the output voltage, the inductor current slew rate can be increased significantly. This patented technique is referred to as “body braking” and is accomplished through the “body braking ...
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IC for voltage positioning and current limit protection. The input offset of this amplifier is calibrated to +/- 1mV in order to reduce the current sense error. The input offset voltage is the primary source of error ...
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CLKIN PHSIN 100% DUTY LATCH PWM_CLK1 CLK Q Q1_100%DUT Y PWMQ1 D 1 EAIN 2 4 EAIN PWM COMPARATOR RMPOUT PHSIN VCC VCC CALIBRATION DACIN-SHARE_ADJ EAIN 100mV 200mV + DACIN - SHARE_ADJ VCCL 0.8V DEBUG OFF (LOW=OPEN) ...
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Over Voltage Protection (OVP) The IR3527 includes over-voltage protection that turns on the low side MOSFET to protect the load in the event of a shorted high-side MOSFET, converter out of regulation, or connection of the converter output to an ...
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Emulated Bootstrap Diode IR3527 integrates a PFET to emulate the bootstrap diode. An external bootstrap diode connected from VCCL pin to BOOST pin can be added to reduce the drop across the PFET but is not needed in most applications. ...
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IC Die Temperature To ensure proper operation, the IC die should never operate at or above 150° C. For the vast majority of applications, the IR3527 dual phase IC will not require any type of heat sink to achieve temperatures ...
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LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout; therefore, minimizing the noise coupled to the IC. x Separate analog bus (EAIN, DACIN, and IOUT) from digital bus (CLKIN, PSI, ...
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PCB Metal and Component Placement x Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be shorting. x Lead land length should be equal to maximum part lead length + 0.3 ...
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Solder Resist x The solder resist should be pulled away from the metal lead lands and center pad by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands ...
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Stencil Design x The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the ...
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PACKAGE INFORMATION 24L MLPQ ( Body) – IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 Page 30.5 C/w JA Data and specifications subject to change without ...