MAX17480GTL+ Maxim Integrated Products, MAX17480GTL+ Datasheet - Page 26

• Manufacturer Part Number: MAX17480GTL+
• Description: IC CTRLR SERIAL VID 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17480GTL+

• Applications: Processor
• Current - Supply: 5mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Output Voltage Range: - 10 V to + 10 V
• Input Voltage Range: 4 V to 26 V
• Input Current: 5 mA
• Power Dissipation: 1778 mW
• Operating Temperature Range: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AMD 2-/3-Output Mobile Serial
VID Controller
When a transient occurs, the output voltage deviation
depends on the controller’s ability to quickly detect the
transient and slew the inductor current. A fixed-frequency
controller typically responds only when a clock edge
occurs, resulting in a delayed transient response. To
minimize this delay time, the MAX17480 includes
enhanced transient detection and transient phase
repeat capabilities. If the controller detects that the out-
put voltage has dropped by 41mV, the transient detec-
tion comparator immediately retriggers the phase that
completed its on-time last. The controller triggers the
subsequent phases as normal, on the appropriate
oscillator edges. This effectively triggers a phase a full
cycle early, increasing the total inductor-current slew
rate and providing an immediate transient response.
The MAX17480 provides an FBAC and FBDC pin for
each SMPS to allow for flexible AC and DC droop set-
tings. FBAC is the output of an internal transconduc-
tance amplifier that outputs a current proportional to the
current-sense signal. FBDC is the feedback input that is
compared against the internal target. Place resistors
and capacitors at the FBAC and FBDC pins as shown
in Figure 5. With this configuration, the DC droop is
always less than or equal to the AC droop.
Figure 5. Core SMPS Feedback Connection
FBDC is the feedback input to the error amplifier.
Based on the configuration in Figure 5, the core SMPS
output voltage is given by:
where the target voltage (V
Nominal Output-Voltage Selection section, and the
FBAC amplifier’s output current (I
by each phase’s current-sense voltage:
26
Core Steady-State Voltage Positioning (DC Droop)
TARGET
V
CSP
CSN
______________________________________________________________________________________
OUT
MAX17480
ERROR
AMP
=
G
V
m(FBAC)
TARGET
FBAC
FBDC
−
R
FBAC
C
FB
R
Adjustment Amplifiers
FBDC
Core SMPS Feedback
R
TARGET
FB
+
Transient Phase Repeat
R
R
R
FBAC
FBDC
×
FBDC
R
FBAC
FBAC
) is defined in the
AGND
+
4700pF
R
) is determined
100Ω
FB
×
I
CORE SENSE_H
FB
A A C
where V
voltage, and G
Electrical Characteristics table. DC droop is typically used
together with the +12.5mV offset feature to keep within the
DC tolerance window of the application. See the Offset
and Address Change for Core SMPSs (OPTION) section.
The ripple voltage on FBDC must be less than the -33mV
(max) transient phase repeat threshold:
where ∆I
effective output ESR at the remote sense point, R
is the current-sense element, and G
(max) as defined in the Electrical Characteristics table.
The worst-case inductor ripple occurs at the maximum
input-voltage and maximum output-voltage conditions:
To make the DC and AC load-lines the same, directly
short FBAC to FBDC.
To disable DC voltage positioning, remove R
connects FBAC to FBDC.
Each of the MAX17480 core supply SMPSs includes one
transconductance amplifier for voltage positioning. The
amplifiers’ inputs are generated by summing their respec-
tive current-sense inputs, which differentially sense the
voltage across either current-sense resistor or the induc-
tor’s DCR.
The voltage-positioning droop amplifier’s output (FBAC)
connects to the remote-sense point of the output
through an RC network that sets each phase’s AC volt-
age-positioning gain:
where the target voltage (V
Nominal Output-Voltage Selection section, Z
effective impedance of C
output current (I
current-sense voltage:
V
R
OUT
FBAC
∆I
+
=
R
L MAX
CS
FBAC
R
Core Transient Voltage-Positioning Amplifier
V
(
FBDC
L
TARGET
R
= V
FBDC
is the inductor ripple current, R
)
+
CSP
m(FBAC)
=
R
FB
≤
V
FBAC
I
R
FBAC
OUT MAX
−
∆
(
FBAC
- V
66
I R
R
L SENSE m FBAC FBDC
FBAC
mV
CSN
(
) is determined by each phase’s
∆
is typically 2mS as defined in the
=
I R
−
2
L SENSE m FBAC
∆
G
FB
is the differential current-sense
)
R
I R
+
V
G
m FBAC CS
L ESR
(
FBAC
IN M
V
R
, and the FBAC amplifier’s
(
TARGET
IN MAX
(
(
FBDC
(
G
A A X SW
)
(
×
R
)
(
)
)
R
FBAC
V
f
R
)
+
m(FBAC)
) is defined in the
−
FBDC
R
L
)
V
FB
+
− 66
OUT MAX
+
R
∆ ∆ I R
F
B B
mV
L ESR
(
(AC Droop)
Z
)
CF
ESR
CFB
is 2.06mS
FB
B B
)
, which
≤
)
I
SENSE
is the
FBDC
is the
33
mV