IR3080MPBF International Rectifier, IR3080MPBF Datasheet
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IR3080MPBF
Specifications of IR3080MPBF
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IR3080MPBF Summary of contents
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TM XPHASE VRD10 CONTROL IC WITH VCCVID & OVERTEMP DETECT DESCRIPTION The IR3080 Control IC combined with an IR XPhase implement a complete VRD 10 power solution. The “Control” IC provides overall system control and interfaces with any number of ...
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... ORDERING INFORMATION Device IR3080MTRPbF IR3080MPbF ABSOLUTE MAXIMUM RATINGS Operating Junction Temperature……………..150 Storage Temperature Range………………….-65 ESD Rating……………………………………..HBM Class 1C JEDEC standard ...
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ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over: 9.5V ≤ ≤ 100 C J PARAMETER VDAC Reference System Set-Point Accuracy Source Current Sink Current VID Input Threshold VID Pull-up Resistors Regulation Detect Comparator Input Offset Regulation ...
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PARAMETER Oscillator Switching Frequency R Peak Voltage (5V typical, measured VBIAS) Valley Voltage (1V typical, measured VBIAS) VBIAS Regulator Output Voltage Current Limit Soft Start and Delay SS/DEL to FB Input Offset Voltage Charge ...
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PARAMETER VCC Under-Voltage Lockout Start Threshold Stop Threshold Hysteresis General VCC Supply Current VIDPWR Supply Current VOSNS- Current VRHOT Comparator HOTSET Bias Current Output Voltage VRHOT Leakage Current Threshold Hysteresis Threshold Voltage (increasing temperature) Note 1: Guaranteed by design, but ...
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PIN DESCRIPTION PIN# PIN SYMBOL PIN DESCRIPTION 1 VIDFB Feedback to the VCCVID regulator. Connect to the VCCVID output. 2 VCCVID 1.2V/150mA Regulator Output. Can also drive external pass transistor to minimize on-chip power dissipation 3 VIDPWR Power for VID ...
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SYSTEM THEORY OF OPERATION TM XPhase Architecture TM The XPhase architecture is designed for multiphase interleaved buck converters which are used in applications requiring small size, design flexibility, low voltage, high current and fast transient response. The architecture can control ...
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PWM Control Method The PWM block diagram of the XPhase trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. An external RC circuit connected to the ...
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VPEAK (5.0V) VPHASE4&5 (4.5V) VPHASE3&6 (3.5V) VPHASE2&7 (2.5V) VPHASE1&8 (1.5V) VVALLEY (1.00V) PWM Operation The PWM comparator is located in the Phase IC. Upon receiving a clock pulse, the PWM latch is set; the PWMRMP voltage begins to increase; the ...
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PHASE IC CLOCK PULSE EAIN PWMRMP VDAC GATEH GATEL STEADY-STATE OPERATION TM Body Braking In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; The ...
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Figure 5. Inductor Current Sensing and Current Sense Amplifier The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled ...
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IR3080 THEORY OF OPERATION Block Diagram The Block diagram of the IR3080 is shown in Figure 6, and specific features are discussed in the following sections. VCC - START + STOP + 9.1V VCC UVLO COMPARATOR VID DELAY 8.9V - ...
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The IR3080 can accept changes in the VID code while operating and vary the DAC voltage accordingly. The sink/source capability of the VDAC buffer amplifier is programmed by the same external resistor that sets the oscillator frequency. The slew rate ...
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Processor Pins (0 = low high) VID4 VID3 VID2 VID1 ...
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Control IC VDAC Inductor DCR Temperature Correction If the thermal compensation of the inductor DCR provided by the temperature dependent gain of the current sense amplifier is not adequate, a negative temperature coefficient (NTC) thermistor can be used for additional ...
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VCC VID Linear Regulator and VID Power Good The IR3080 integrates a fully protected 1.2V/150mA VCCVID linear regulator with over-current protection. Power for the VCCVID regulator is drawn from the VIDPWR pin which is typically connected to a 3.3V supply. ...
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The over-current delay can be reduced by adding a resistor in series with the SS/DEL capacitor. The delay comparator’s offset voltage is reduced by the drop in the resistor caused by the discharge current. The value of the series resistor ...
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VID = 11111X Fault VID codes of 111111 and 111110 will set the fault latch and disable the error amplifier. An 800ns delay is provided to prevent a fault condition from occurring during Dynamic VID changes. Power Good Output The ...
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APPLICATION INFORMATIONS 12V RVCC 10 ohm CVCC 0.1uF RHOTSETC1 1nF 1 VIDFB VCC 2 VCCVID VBIAS 3.3V 3 VIDPWR BBFB IR3080 VID5 4 VID5 EAOUT CONTROL VID0 5 VID0 FB IC VID1 6 VID1 VDRP VID2 7 VID2 IIN VID3 ...
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DESIGN PROCEDURES - IR3080 AND IR3086A CHIPSET IR3080 EXTERNAL COMPONENTS Oscillator Resistor Rosc The oscillator of IR3080 generates a triangle waveform to synchronize the phase ICs, and the switching frequency of the each phase converter equals the oscillator frequency, which ...
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DEL = t SSDEL VDAC Slew Rate Programming Capacitor C The slew rate of VDAC down-slope SR Equation (8), where I is the sink current of VDAC pin as shown in Figure 15. The resistor R ...
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No Load Output Voltage Setting Resistor R A resistor between FB pin and the converter output is used to create output voltage offset V difference between V voltage and output voltage at no load condition. Adaptive voltage positioning further DAC ...
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Measure the inductance L and the inductor DC resistance R follows The bias current flowing out of the non-inverting input of the current sense amplifier creates a voltage drop across ...
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Combined Over Temperature and Phase Delay Setting Resistors R The over temperature setting resistor divider can be combined with the phase delay resistor divider to save one resistor per phase. Calculate the HOTSET threshold voltage V Equation (23). If the ...
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RCP RFB VO VDAC RDRP VDRP (a) Type II compensation π ∗ ∗ optional and may be needed ...
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∗ optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A CP1 ...
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DESIGN EXAMPLE 1 - VRD 10 CONVERTER SPECIFICATIONS Input Voltage DAC Voltage: V =1.35 V DAC No Load Output Voltage Offset: V Output Current: I =105 ADC O Maximum Output Current: I =120 ADC OMAX Output ...
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The power good delay time is − − DEL VccPG I CHG VDAC Slew Rate Programming Capacitor C From Figure 15, the sink ...
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365 MAX CS _ MIN = = R DRP ∗ Control IC Over Temperature Setting Resistors R Set the temperature threshold at 115 ºC, which corresponds to the IC ...
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The phase delay resistor ratios for phases 400kHz of switching frequencies are RA RA =0.415, RA =0.202, RA PHASE2 PHASE3 slope. Pre-select R =R PHASE11 PHASE21 RA = PHASE 1 ∗ PHASE 12 ...
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DESIGN EXAMPLE 2 - EVRD 10 HIGH FREQUENCY ALL-CERAMIC CONVERTER SPECIFICATIONS Input Voltage DAC Voltage: V =1.3 V DAC No Load Output Voltage Offset: V Output Current: I =105 ADC O Maximum Output Current: I =120 ...
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The power good delay time is ∗ − − DEL VccPG I CHG VDAC Slew Rate Programming Capacitor C From Figure 15, the sink ...
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162 MAX CS _ MIN = = R DRP ∗ Control IC Over Temperature Setting Resistors R Set the temperature threshold at 115 ºC, which corresponds the IC die ...
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The over temperature setting voltage of phases and 6 is lower than the phase delay setting voltage, VBIAS*RA Pre-select R PHASEx. PHASE11 ∗ − PHASEx BIAS HOTSET R PHASEx 2 ∗ − ...
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RAMP = ∗ ∗ ∗ 100 * ...
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LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. • Dedicate at least one middle layer for a ground plane LGND. • ...
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PCB Metal and Component Placement • Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. • Lead land length should be equal to maximum part ...
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Solder Resist • The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non ...
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Stencil Design • The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the ...
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TYPICAL PERFORMANCE CHARACTERISTICS Page 40 Figure 13 - Oscillator Frequency versus ROSC 1000 950 900 850 800 750 700 650 600 550 500 450 400 350 300 250 200 150 ...
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PACKAGE INFORMATION 32L MLPQ ( Body) – θ IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 Page C/W, θ JA Data and specifications subject to change without ...