IR3080MPBF International Rectifier, IR3080MPBF Datasheet - Page 13
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IR3080MPBF
Manufacturer Part Number
IR3080MPBF
Description
IC PHASE CONTROLLER 32MLPQ
Manufacturer
International Rectifier
Series
XPhase™r
Datasheet
1.IR3080MTRPBF.pdf
(41 pages)
Specifications of IR3080MPBF
Applications
Processor
Current - Supply
11mA
Voltage - Supply
9.5 V ~ 14 V
Operating Temperature
0°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
32-MLPQ
Package
32-Lead MLPQ
Circuit
X-Phase Control IC
Switch Freq (khz)
150kHz to 1.0MHz
Pbf
PbF Option Available
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The IR3080 can accept changes in the VID code while operating and vary the DAC voltage accordingly. The
sink/source capability of the VDAC buffer amplifier is programmed by the same external resistor that sets the
oscillator frequency. The slew rate of the voltage at the VDAC pin can be adjusted by an external capacitor between
VDAC pin and the VOSNS- pin. A resistor connected in series with this capacitor is required to compensate the
VDAC buffer amplifier. Digital VID transitions result in a smooth analog transition of the VDAC voltage and
converter output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output
voltage.
It is desirable to prevent negative inductor currents in response to a request for a lower VID code. Negative current
transforms the buck converter into a boost converter and transfers energy from the output capacitors back into the
input voltage. This energy can cause voltage spikes and damage the silver box or other components unless they
are specifically designed to handle it. Furthermore, power is wasted during the transfer of energy from the output
back to the input.
The IR3080 includes circuitry that turns off both control and synchronous MOSFETs in response to a lower VID
code so that the load current instead of the inductor discharges the output capacitors. A lower VID code is detected
by the VID step-down detect comparator which monitors the “fast” output of the DAC (plus 7mV for noise immunity)
compared to the “slow” output of the VDAC pin. If a dynamic VID step down is detected, the body brake latch is set
and the output of the error amplifier is pulled down to 75% of the DAC voltage by the VID body brake clamp. This
triggers the Body Braking
The converter’s output voltage needs to be monitored and compared to the VDAC voltage to determine when to
resume normal operation. Unfortunately, the voltage on the FB pin can be pulled down by its compensation network
during the sudden decrease in the Error Amplifier’s output voltage so an additional pin BBFB is provided. The BBFB
pin is connected to the converter output voltage and VDRP pin with resistors of the same value as on the FB pin
and therefore provides an un-corrupted representation of converter output voltage. The regulation detect
comparator compares the BBFB to the VDAC voltage and resets the body brake latch releasing the error amplifier’s
output and allowing normal operation to resume. Body Braking
disabled by connecting the BBFB pin to ground.
VIDPWR
VOSNS-
EAOUT
Page 13
VID5
VID0
VID1
VID2
VID3
VID4
TO ERROR AMP
VID DOWN
BB CLAMP
ENABLE
700
TM
BODY
BRAKE
LATCH
0.6V
+
-
function, which turns off both high side and low side drivers in the phase ICs.
VID INPUT
COMPARATORS
(1 OF 6 SHOWN)
+
-
75%
S
R
+
-
1.7us
BLANKING
Figure 7. VID Control Block Diagram
DIGITAL TO
ANALOG
CONVERTER
VID STEP-DOWN
DETECT
COMPARATOR
+
-
REGULATION
DETECT
COMPARATOR
7mV
"FAST" VDAC
-
+
-
+
+
-
TM
during a transition to a lower VID code can be
+
-
IROSC (From Current Source Generator)
VDAC BUFFER
AMP
ISOURCE
ISINK
IBBFB
800ns
BLANKING
"SLOW" VDAC
IR3080PbF
VID = 11111X DETECT
BBFB
VDAC